Semiconductor bonding and layer transfer method

• US 20050280155A1
• Filed: 03/29/2005
• Published: 12/22/2005
• Est. Priority Date: 06/21/2004
• Status: Abandoned Application

• Current Assignee: BeSang Inc.
• Original Assignee: BeSang Inc.
• Inventors: Lee, Sang-Yun
• Application Number:
  US11/092,501
• Publication Number:
  US 20050280155A1
• Time in Patent Office: Days
• US Class Current: 257/758
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 Argon [Ar]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01031 : Gallium [Ga]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01038 : Strontium [Sr]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01056 : Barium [Ba]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01093 : Neptunium [Np]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H10B 10/00 : Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/10 : SRAM devices comprising bipolar components
• CPC Class Codes: H10B 10/18 : Peripheral circuit regions
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels

Abstract

The present invention provides a method of coupling substrates together. The method includes providing first and second substrates and then coupling the first and second substrates together. One of the first and second substrates includes devices with an interconnect region positioned thereon and the other substrate carries a device structure.

Claims

1. A method of forming circuitry comprising:

providing a first substrate with electronic devices formed thereon;

providing an interconnect region on a surface of the first substrate, the interconnect region having conductive interconnects and vias extending therethrough;

providing a second substrate with a device structure positioned thereon, the device structure including a stack of semiconductor layers; and

coupling the device structure to the interconnect region.

2. The method of claim 1 further including providing a contact region so that the device structure and interconnect region are coupled together through the contact region.

3. The method of claim 2 wherein the contact region includes at least one of a conductive glue layer, a conductive layer, and a silicide layer.

4. The method of claim 2 further including providing a dielectric region on the device structure so that the device structure and interconnect region are coupled together through the first contact region and the dielectric region.

5. The method of claim 1 wherein the step of coupling the device structure to the interconnect region includes providing heat to them.

6. The method of claim 1 wherein the step of providing the interconnect region includes providing a blocking region positioned to reduce the flow of contaminants therethrough.

7. The method of claim 1 further including removing at least a portion of the second substrate from the device structure.

8. The method of claim 1 further including providing a detaching layer carried by the second substrate, the detaching layer extending proximate to the device structure.

9. The method of claim 8 further including removing the second substrate from the device structure by separating them along the detaching layer.

10. The method of claim 1 further including providing the stack of semiconductor layers on the donor substrate has at least one single crystalline semiconductor layer.

11. A method of forming a circuit comprising:

providing a handle substrate;

providing a donor substrate with a device structure positioned thereon, the device structure including a stack of semiconductor layers;

coupling the first and second substrates together;

removing the donor substrate from the first device structure so that the first device structure is carried by the handle substrate;

providing an acceptor substrate which carries an interconnect region, the interconnect region being electrically coupled to electronic devices carried by the acceptor substrate;

coupling the first device structure and interconnect region together; and

removing the handle substrate and the first and second dielectric regions.

12. The method of claim 11 further including providing a contact region so that, after the donor wafer is removed, the first device structure and interconnect region are coupled together through the contact region.

13. The method of claim 11 wherein the step of providing the interconnect region includes providing a blocking region positioned to reduce the flow of contaminants therethrough.

14. The method of claim 11 further including etching portions of the device structure to form at least one electrical device, the electrical device(s) being coupled to the electronic devices carried by the acceptor wafer through the interconnect region.

15. A method of forming a circuit comprising:

providing a first substrate;

positioning an interconnect region on a surface of the first substrate, the interconnect region having conductive interconnects and vias extending therethrough;

providing a second substrate;

positioning a device structure on a surface of the second substrate, the device structure including a stack of doped semiconductor material layers; and

coupling the device structure to the interconnect region.

16. The method of claim 15 further including forming electronic devices near the surface of the first substrate.

17. The method of claim 15 wherein the step of coupling the device structure to the interconnect region includes providing heat to them.

18. The method of claim 15 wherein the step of providing the interconnect region includes providing a blocking region positioned therein to reduce the flow of oxygen therethrough.

19. The method of claim 15 further including processing the device structure to form at least one memory device therewith.

20. The method of claim 15 further including removing the second substrate from the device structure after the device structure has been coupled to the interconnect region.