Semiconductor device with base support structure

• US 20050280156A1
• Filed: 07/12/2005
• Published: 12/22/2005
• Est. Priority Date: 06/21/2004
• Status: Active Grant

• Current Assignee: BeSang Inc.
• Original Assignee: BeSang Inc.
• Inventors: Lee, Sang-Yun
• Granted Patent: US 8,779,597 B2
• Time in Patent Office: Days
• US Class Current: 257/758
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 Argon [Ar]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01038 Strontium [Sr]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01049 Indium [In]
• CPC Class Codes: H01L 2924/01056 Barium [Ba]
• CPC Class Codes: H01L 2924/01073 Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels

Abstract

An apparatus includes a semiconductor chip with a base support structure having a surface and an opposed surface. At least one device structure extends from the surface of the base support structure. A first conductive region is coupled to the base support structure. At least a portion of the first conductive region extends below the opposed surface.

Claims

1. Apparatus, comprising:

a base support structure with a surface and an opposed surface;

a device structure extending from the surface of the base support structure; and

a first conductive region in communication with the base support structure or the device structure wherein at least a portion of the first conductive region extends below the opposed surface.

2. The apparatus of claim 1, further including a second conductive region extending from the other of the base support structure and the device structure.

3. The apparatus of claim 2, wherein at least a portion of the second conductive region extends below the opposed surface of the base support structure.

4. The apparatus of claim 1, wherein the device structure includes a material stack at least partially surrounded with an insulator region and a control terminal, the insulator region being adjacent to the material stack.

5. The apparatus of claim 4, wherein the conductivity of the material stack is adjustable in response to a signal provided to the control terminal.

6. The apparatus of claim 1, further including an electronic circuit positioned below the opposed surface of the base support structure, the electronic circuit being coupled to the first conductive region.

7. An apparatus, comprising:

an interconnect region;

a base support structure carried by the interconnect region;

a plurality of device structures extending upwardly from a surface of the base support structure;

a first conductive region in communication with the base support structure ; and

a second conductive region in communication with at least one device structure.

8. The apparatus of claim 7, wherein the dimension of the bottom surface of at least one device structure is different from the dimension of its corresponding top surface.

9. The apparatus of claim 7, further including an electronic circuit in communication with the base support structure and corresponding device structure through the first and second conductive regions, respectively, at least one of the first and second conductive regions extending through the interconnect region.

10. The apparatus of claim 7, wherein at least one device structure includes a material stack and first and second control terminals, the first and second control terminals being spaced from the material stack by first and second insulator regions, respectively.

11. The apparatus of claim 10, wherein at least one device structure operates as a memory device.

12. The chip of claim 7, wherein the base support structure is bonded to the interconnect region.

13. An apparatus, comprising:

a substrate which carries electronic circuitry;

an interconnect region carried by the substrate;

a base support structure carried by the interconnect region;

one or more device structure(s) carried by the base support structure;

a first conductive region extending from the base support structure; and

a second conductive region in communication with a corresponding device structure and the electronic circuitry.

14. The apparatus of claim 13, further including a metal region which bonds the base support structure and the interconnect region together.

15. The apparatus of claim 14, wherein the first conductive region is in communication with the base support structure through the metal region.

16. The apparatus of claim 13, wherein one or more device structures includes an insulator region at least partially surrounding its sidewall and a control terminal at least partially surrounding the insulator region.

17. The apparatus of claim 16, wherein the conductivity of the device structure(s) is adjustable in response to a signal provided to its corresponding control terminal.

18. The apparatus of claim 13, wherein the base support structure or at least one of the device structures includes crystalline semiconductor material.

19. The apparatus of claim 13, wherein at least one device structure includes a semiconductor material of a first conductivity type carried by a semiconductor material of a second conductivity type.

20. The apparatus of claim 13, wherein the first conductive region operates as a current return.