Efficiency improvement of DC-DC converter

• US 20050280401A1
• Filed: 06/22/2004
• Published: 12/22/2005
• Est. Priority Date: 06/22/2004
• Status: Active Grant

• Current Assignee: Dialog Semiconductor GmbH (Renesas Electronics Corporation)
• Original Assignee: Dialog Semiconductor GmbH (Renesas Electronics Corporation)
• Inventors: Plankensteiner, Manfred
• Granted Patent: US 7,015,678 B2
• Time in Patent Office: Days
• US Class Current: 323/222
• CPC Class Codes: H02M 1/0032 Control circuits allowing low power mode operation, e.g. in standby mode
• CPC Class Codes: H02M 1/088 for the simultaneous control of series or parallel connected semiconductor devices
• CPC Class Codes: H02M 3/1584 with a plurality of power processing stages connected in parallel
• CPC Class Codes: H03K 17/122 in field-effect transistor switches
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

Actual switching DC-DC converters have disadvantages in specific operating regions due to different reasons for power losses. Large switching transistors provide favorable efficiency at high output currents, but need high currents to charge/discharge the switching transistor'"'"'s gate, resulting in poor efficiency at low output currents. Small transistors are more efficient at low currents, but are poor at high currents. The disclosed invention changes the size of the MOSFET switching transistors proportional to the output current, thus combining the efficiency of small transistors at low output currents and of large transistors at high output currents.

Claims

1. A circuit implementing an efficiency improved DC-DC converter, comprising

means for the basic circuit functions of a DC-DC converter;

means for one or more MOSFET switching transistor arrangements, implementing variable size switching transistors;

means for sensing a current as a measure for the converter output current;

means to generate a control signal, intended to select the desired size of said variable size MOSFET transistors, based on said measure for the converter output current; and

means for a selection mechanism to activate the appropriate transistor elements to finally realize said variable size MOSFET transistors with the desired size.

2. The circuit of claim 1 wherein the means for the basic circuit functions of a DC-DC converter implements a buck converter, using means for a NMOS switching transistor arrangement and means for a PMOS switching transistor arrangement, each implementing a variable size MOSFET transistor.

3. The circuit of claim 1 wherein the means for the basic circuit functions of a DC-DC converter implements a boost converter, using means for either a NMOS switching transistor arrangement or means for a PMOS switching transistor arrangement, implementing a variable size MOSFET transistor.

4. The circuit of claim 1 wherein the means for a current sensor are positioned in the converter output current path to measure the DC output current.

5. The circuit of claim 1 wherein the means for a current sensor are positioned in series with the switching transistors.

6. The circuit of claim 5 wherein the resulting signal of said means for a current sensor, which are positioned in series with the switching transistors, are then passed to means for an integrator function.

7. The circuit of claim 6 wherein said means for an integrator function integrate the measured current typically over a period of 1 to 50 power converter pulses.

8. The circuit of claim 1 wherein the means to generate a control signal, intended to select the desired size of said variable size MOSFET transistors, based on said measure for the converter output current, provide a proportional relation between said converter output current and said variable size MOSFET transistors.

9. The circuit of claim 1 wherein the means for a MOSFET switching transistor arrangement, implementing variable size switching transistors is implemented as the parallel connection of typically 2 to 8 individual MOSFET transistors, where said individual MOSFET transistors are parallel connected at their source and their drain and where their gates are connected to said means for a selection mechanism to activate the appropriate transistor elements.

10. The circuit of claim 9 wherein said variable size MOSFET transistor, which is implemented as the parallel connection of individual MOSFET transistors uses MOSFET transistors of the same size.

11. The circuit of claim 9 wherein said variable size MOSFET transistor, which is implemented as the parallel connection of individual MOSFET transistors uses MOSFET transistors of the different sizes, for example with the size in binary steps 1, 2, 4, 8 etc.

12. The circuit of claim 9 wherein said variable size MOSFET transistor, which is implemented as the parallel connection of individual MOSFET transistors uses MOSFET transistors of different sizes, specifically designed to match a non-linear stepping curve, like a logarithmic curve.

13. The circuit of claim 1 wherein the means for a MOSFET switching transistor arrangement, implementing variable size switching transistors is implemented as a MOSFET transistor with a single source region and a single drain region, but with several, typically 2 to 8, individual gate regions, and where said individual gates are connected to said means for a selection mechanism to activate the appropriate transistor elements.

14. The circuit of claim 13 wherein said variable size MOSFET transistor, which is implemented as a MOSFET transistor with a single source region and a single drain region, but with several individual gate regions, implements said individual gate regions with the same size.

15. The circuit of claim 13 wherein said variable size MOSFET transistor, which is implemented as a MOSFET transistor with a single source region and a single drain region, but with several individual gate regions, implements said individual gate regions with different sizes, for example with the size in binary steps 1, 2, 4, 8 etc.

16. The circuit of claim 13 wherein said variable size MOSFET transistor, which is implemented as a MOSFET transistor with a single source region and a single drain region, but with several individual gate regions, implements said individual gate regions with different sizes, specifically designed to match a non-linear stepping curve, like a logarithmic curve.

17. A method to improve the efficiency of a DC-DC converter, comprising means for the basic circuit functions of a DC-DC converter, means for one or more variable size MOSFET transistors, means for sensing a current as a measure for the converter output current, means to generate a control signal, intended to select the desired size of said variable size MOSFET transistors, depending on a measure of the output current of said DC-DC converter and means for a selection mechanism to activate the appropriate transistor elements to finally build said variable size MOSFET transistors with the desired size;

providing a measure of the output current of said DC-DC converter;

generating a control signal based on said output current of said DC-DC converter to change the sizes of said means for one or more variable size MOSFET transistors; and

selecting the size of said one or more variable size MOSFET transistors according to said converter output current, i.e. increasing the sizes of said means for variable size MOSFET transistors, when said control signal indicates that said output current of said DC-DC converter increases and decreasing the sizes of said means for variable size MOSFET transistors, when said control signal indicates that said output current of said DC-DC converter decreases.

18. The method of claim 17 wherein providing a measure of the output current of said DC-DC converter measures the output current of said DC-DC converter itself.

19. The method of claim 17 wherein providing a measure of the output current of said DC-DC converter indirectly measures the output current of said DC-DC converter by sensing the switching transistor current and integrating its value over a specific time interval to derive a value representing said converter output current.

20. The method of claim 19 wherein integrating said current value, measured at said switching transistor, over a specific time interval typically integrates over a period of 1 to 50 power converter pulse cycles.

21. The method of claim 17 wherein changing the size of said variable size MOSFET transistor according to said converter output current, follows said converter output current proportionally.

22. The method of claim 17 wherein selecting the size of said one or more variable size MOSFET transistors according to said converter output current selects the size in equal steps, switching on one more of the equally sized transistor elements within said variable size MOSFET transistor.

23. The method of claim 17 wherein selecting the size of said one or more variable size MOSFET transistors according to said converter output current selects the size in equal steps, switching on a binary combination of the transistor elements within said variable size MOSFET transistor, that have sizes in binary steps i.e. 1, 2, 4 etc.

24. The method of claim 17 wherein selecting the size of said one or more variable size MOSFET transistors according to said converter output current selects the size in equal steps, switching on one more of the equally sized transistor elements within said variable size MOSFET transistor.

25. The method of claim 17 wherein selecting the size of said one or more variable size MOSFET transistors according to said converter output current selects the size in non-equal steps, switching on a variable combination of the non-equally sized transistor elements within said variable size MOSFET transistor, that have various sizes, specifically designed to match a non-linear stepping curve, like a logarithmic curve.