Versatile system for accelerated stress characterization of semiconductor device structures
First Claim
1. Circuitry performing accelerated stress characterization of a given transistor, the circuitry comprising:
- a plurality of inverter circuits, formed from the given transistor, disposed in series with one another;
a plurality of signal taps, each respectively and operatively associated with one gap between adjacent inverter circuits in the series thereof;
selective circuitry, operatively coupled to the plurality of signal taps and adapted to select a first and a second of the plurality of signal taps;
a controlled voltage component, operatively coupled the plurality of inverter circuits and adapted to supply a desired supply voltage thereto;
a controlled signal component, operatively coupled the plurality of inverter circuits and adapted to supply a signal of a desired frequency thereto; and
an evaluation component, adapted to receive signal data from the first and second signal taps.
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Abstract
The present invention provides a system (200) for performing accelerated stress characterization of a given transistor (204). Inverter circuits, formed from the given transistor, are disposed in series with one another (202). A plurality of signal taps is operatively associated with each gap between adjacent inverter circuits. Selective circuitry is operatively coupled to the plurality of signal taps, and adapted to output (206) data from a first and a second of the plurality of signal taps. A controlled voltage component (212) is operatively coupled the plurality of inverter circuits, and adapted to supply a desired supply voltage. A controlled signal component (210) is operatively coupled the plurality of inverter circuits, and adapted to supply a signal of a desired frequency thereto. An evaluation component (208) receives signal data from the first and second signal taps for evaluation or processing.
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Citations
20 Claims
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1. Circuitry performing accelerated stress characterization of a given transistor, the circuitry comprising:
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a plurality of inverter circuits, formed from the given transistor, disposed in series with one another;
a plurality of signal taps, each respectively and operatively associated with one gap between adjacent inverter circuits in the series thereof;
selective circuitry, operatively coupled to the plurality of signal taps and adapted to select a first and a second of the plurality of signal taps;
a controlled voltage component, operatively coupled the plurality of inverter circuits and adapted to supply a desired supply voltage thereto;
a controlled signal component, operatively coupled the plurality of inverter circuits and adapted to supply a signal of a desired frequency thereto; and
an evaluation component, adapted to receive signal data from the first and second signal taps. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method of characterizing performance of a given transistor, the method comprising the steps of:
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providing a plurality of inverter circuits, formed from the given transistor, disposed in series with one another;
providing a plurality of signal taps, each respectively and operatively associated with one gap between adjacent inverter circuits in the series thereof;
providing selective circuitry, operatively coupled to the plurality of signal taps and adapted to select a first and a second of the plurality of signal taps;
supplying a fixed frequency source signal to the plurality of inverter circuits;
supplying a first supply voltage to the plurality of inverter circuits;
compiling a first set of signal data from the first and second signal taps;
supplying a second supply voltage to the plurality of inverter circuits;
compiling a second set of signal data from the first and second signal taps; and
processing the first and second sets of signal data to determine a desired transistor performance characteristic. - View Dependent Claims (15, 16, 17, 18, 19)
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20. A semiconductor device characterization system comprising:
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an evaluation structure, comprising an arrangement of one or more sample devices;
a first control component, operatively coupled to the evaluation structure and adapted to control a first operational parameter of the evaluation structure;
a second control component, operatively coupled to the evaluation structure and adapted to control a second operational parameter of the evaluation structure independent of any variance in the first operational parameter; and
an evaluation component, adapted to receive and compile data from the evaluation structure as either the first or second operational parameters are varied.
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Specification