Analog to digital converter calibration via synchronous demodulation

• US 20050280565A1
• Filed: 06/17/2004
• Published: 12/22/2005
• Est. Priority Date: 06/17/2004
• Status: Active Grant

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Kenet LLC (Renesas Electronics Corporation)
• Inventors: Anthony, Michael P., Kushner, Lawrence J.
• Granted Patent: US 7,106,230 B2
• Time in Patent Office: Days
• US Class Current: 341/120
• CPC Class Codes: H03M 1/0682 using a differential network structure, i.e. symmetrical with respect to ground
• CPC Class Codes: H03M 1/1061 using digitally programmable trimming circuits
• CPC Class Codes: H03M 1/44 Sequential comparisons in series-connected stages with change in value of analogue signal

Abstract

A technique for dynamically calibrating a successive approximation charge to digital converter by toggling at least some portion of the converter between two predetermined states, with the design goal of balancing the voltage and/or charge that is output in the two states. The two states are chosen such that they are expected to generate the same output voltage when the converter is in normal operation mode. If there is an imbalance, switching between the two calibration states invariably generates a square wave signal that toggles between two distinct values. A synchronous demodulator having a bandwidth centered at the toggle frequency can then be used to accurately detect an amount of error, which is then feedback to generate correction signals. The detected value of the error signal can in turn can be further integrated over time, to provide a correction value. If there are undesirable static offsets introduced by the synchronous demodulator or by the signal and/or charge levels output by the two differential halves of the converter, a properly timed latch can be used to further stabilize the error signal.

Claims

1. A method for calibrating a digital converter comprising the steps of:

toggling at least some portion of the converter between at least two predetermined calibration states in a calibration mode, with each of the two predetermined calibration states providing a predetermined output signal;

providing a converter output signal over a sequence of multiple predetermined calibration states; and

synchronously demodulating the converter output signal.

2. A method as in claim 1 wherein each of predetermined calibration states provide nominally the same converter output signal.

3. A method as in claim 1 wherein the toggle step is performed at a state toggle frequency and a bandwidth of the synchronous demodulating step is centered at the state toggle frequency.

4. A method as in claim 1 additionally comprising:

using the demodulated converter output signal to provide a correction signal to the converter.

5. A method as in claim 1 wherein the converter is a successive approximation converter.

6. A method as in claim 1 wherein the converter is a complimentary type converter having two conversion signal paths therein, with a first conversion signal path operating as a plus signal path and a second path operation as a minus signal path.

7. A method as in claim 6 wherein

a first one of the two predetermined calibration states is provided by applying a first set of calibration inputs to the plus signal path and a second set of calibration inputs to the minus signal path;

and

a second one of the two predetermined calibration states is provided by applying the same second set of calibration inputs to the plus signal path and the same first set of calibration inputs to the minus signal path.

8. A method as in claim 1 wherein the step of synchronously demodulating further comprises:

integrating the converter output signal to provide an error signal.

9. A method as in claim 8 wherein the error signal is generally a ramp type waveform in the absence of noise.

10. A method as in claim 9 wherein offset voltages introduced by the converter superimpose a sawtooth type waveform on the ramp waveform.

11. A method as in claim 10 additionally comprises:

latching the integrated demodulated signal, in synchronism with the change of state of the converter, to produce the error signal.

12. A method as in claim 7 wherein a common reference input, Vcm, is fed to the plus signal path and the minus signal path.

13. A method as in claim 7 wherein a number of stages used by the digital converter in the calibration mode is at least one stage greater than the number of stages of the converter used in a normal operation mode.

14. A method as in claim 6 wherein two conversion signal paths are pipelined Charge Coupled Device (CCD) stages.

15. A method as in claim 14 wherein the calibration inputs are fed to a respective set of adjustable charge splitters, with a charge splitter associated with a corresponding one of the pipeline stages.

16. A method as in claim 15 additionally comprising:

generating an error signal from the synchronously demodulated output signal; and

deriving adjustment signals for controlling the adjustable splitters from the error signal.

17. A method as in claim 1 additionally comprises:

chopper stabilizing at least one component of the digital converter during a normal operating mode.

18. A method as in claim 17 additionally comprising:

while in the calibration mode, operating a portion of a circuit used in the chopper stabilizing step as part of the synchronous demodulating step.