Display panel driver unit

• US 20050280653A1
• Filed: 06/03/2005
• Published: 12/22/2005
• Est. Priority Date: 06/03/2004
• Status: Active Grant

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Tsukamoto, Akihito
• Granted Patent: US 7,425,961 B2
• Time in Patent Office: Days
• US Class Current: 345/558
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory

Abstract

To provide an inexpensive display panel driver unit with a built-in memory, which is capable of achieving the same operation as that obtained in using a dual port memory by employing a single port RAM without reduction in an operation speed. A reservation buffer 14 for storing an address and data in a memory writing is provided. When a display reading and a memory writing occurs simultaneously and row addresses of the memory writing and the display reading agree with each other, the memory writing is executed and also read data from addresses except a write address together with write data into the write address are used as data of the display reading. Also, when the row addresses of the memory writing and the display reading are different from each other, the write address and data are stored in the reservation buffer and also the display reading is executed. The similar mediation is applied in executing the reserved writing.

Claims

1. A display panel driver unit, having a built-in memory that is able to read one line data of a display screen collectively in a display reading operation, comprising:

a reservation buffer, storing a write address and write data when a memory writing is generated from a host device of the memory; and

a mediator, executing mediation between the memory writing and the display reading;

wherein, when the display reading and the memory writing occurs simultaneously and a row address of the memory writing agrees with a row address of the display reading, the mediator executes the memory writing into the write address of the memory cell and also executes the display reading by reading the data from addresses of the memory cell except the write address and using the write data into the write address as read data from the write address,

when the display reading and the memory writing occurs simultaneously and the row address of the memory writing is different from the row address of the display reading, the mediator stores the write address and the write data in the reservation buffer as a write reservation and also executes the display reading,

when the write address and the write data are stored in the reservation buffer as the write reservation and also the memory writing into a same row address as the write address for which the write reservation is made occurs, the mediator executes simultaneously the memory writing occurred and the memory writing held by the write reservation collectively, and

when the write address and the write data are stored in the reservation buffer as the write reservation and also the display reading from a same row address as the write address for which the write reservation is made occurs, the mediator executes the memory writing into the write address, for which the write reservation is made, of the memory cell and also executes the display reading by reading the data from write addresses of the memory cell except the write address for which the write reservation is made and using the write data into the write address, for which the write reservation is made, as read data from the write address for which the write reservation is made.

2. The display panel driver unit according to claim 1, wherein the reservation buffer is constructed by a FIFO memory that stores the row address and a column address of the memory writing and the write data, and the row address of the display reading or the row address of the memory writing is compared with the row address being output from the FIFO memory to decide whether or not the write reservation is made.

3. The display panel driver unit according to claim 1, wherein the reservation buffer includes:

a register buffer, for inputting the row address of the display reading or the row address of the memory writing and then outputting a presence or absence of the write reservation; and

a reservation memory, for storing the column address of the memory writing and the write data by receiving the row address of the display reading or the row address of the memory writing as an input.

4. The display panel driver unit according to claim 1, wherein the memory includes memory cells arranged vertically and horizontally and designated by the row address and the column address, bit lines from which the data of the memory cells are read in response to the row address in the display reading and the memory writing, a precharge circuit for setting the bit lines to a fixed electric potential as occasion demands, a first bit-line driving circuit for driving the bit line of the memory cell having the column address in response to the memory writing occurred, and a second first bit-line driving circuit for driving the bit line of the memory cell having the column address in response to the memory writing for which the write reservation is made.