Processing pipeline of pixel data of a color image acquired by a digital sensor

• US 20050280725A1
• Filed: 04/29/2005
• Published: 12/22/2005
• Est. Priority Date: 06/11/2004
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Pappalardo, Francesco, Capra, Alessandro, Spampinato, Giuseppe, Fodera, Paolo Antonino, Virlinzi, Francesco
• Granted Patent: US 7,397,944 B2
• Time in Patent Office: Days
• US Class Current: 348/272
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 3/4015 Image demosaicing, e.g. colour filter arrays [CFA] or Bayer patterns

Abstract

A color image processing pipeline performs an interpolation on color data to generate triplets located at distinct pixel locations. The pipeline includes defect correction and image enhancement blocks having a first color interpolation block for generating RGB information for each pixel of an input image pixel pattern, and a second color interpolation block for receiving the RGB information to provide enhanced RGB pattern pixels. Dedicated line memories and delay circuits associated with the defect correction and image enhancement blocks permit real-time processing of pixel data. First and second read/write buffers store a subset or pixel block of the image data, and invert a scanning mode of pixel data being fed to the dedicated line memories and delay circuits associated to at least the first color interpolation block, from row-wise to column-wise, for each subset of data to be stored therein.

Claims

1-6. -6. (canceled)

7. A color image processing pipeline for performing, among corrective and image enhancement steps, at least an interpolation on color data to generate triplets located at distinct pixel locations, the pipeline comprising:

a plurality of defect correction and image enhancement blocks comprising at least a first color interpolation block generating RGB information for each pixel of an input image pixel pattern, and a second color interpolation block receiving the RGB information from said first color interpolation block and providing enhanced RGB pattern pixels;

a plurality of dedicated line memories and delay circuits associated with said plurality of defect correction and image enhancement blocks for permitting real-time processing of pixel data; and

first and second read/write buffers having an identical capacity for storing a subset or pixel block of the image data, and for inverting a scanning mode of pixel data being fed to said plurality of dedicated line memories and delay circuits associated to at least said first color interpolation block, from row-wise to column-wise, for each subset of data to be stored therein.

8. A color image processing pipeline according to claim 7, wherein for given dimensions of a processed subset or block of pixels to be output by the pipeline, the dimensions of the subset or pixel block of image data respectively written in and read from said first and second read/write buffers correspond to:

X*SF_hor+OV_hor, and

Y*SF_ver+OV_ver

with SF being a scaling factor in the respective dimension, and OV being a measure of the computational overhead in the respective dimension corresponding to the number of lines and columns that are lost in the pipeline, and which is null for the horizontal dimension because of the translation of the scanning mode of said pair of first and second read/write buffers when feeding pixel data to the pipeline.

9. A color image processing pipeline according to claim 7, wherein the given dimensions of the processed subset or block of pixels to be output by the pipeline are 16*16.

10. A color image processing pipeline comprising:

a plurality of defect correction and image enhancement blocks comprising a first color interpolation block generating RGB information for each pixel of an input image pixel pattern, and a second color interpolation block receiving the RGB information from said first color interpolation block and providing enhanced RGB pattern pixels;

a plurality of dedicated line memories and delay circuits associated with said plurality of defect correction and image enhancement blocks for permitting real-time processing of pixel data; and

first and second buffers for storing a subset or pixel block of the image data, and for inverting a scanning mode of pixel data being fed to said plurality of dedicated line memories and delay circuits associated to at least said first color interpolation block, from row-wise to column-wise, for each subset of data to be stored therein.

11. A color image processing pipeline according to claim 10, wherein said first and second buffers comprise read/write buffers.

12. A color image processing pipeline according to claim 10, wherein said first and second buffers are the same size.

13. A color image processing pipeline according to claim 10, wherein for given dimensions of a processed subset or block of pixels to be output by the pipeline, the dimensions of the subset or pixel block of image data respectively written in and read from said first and second buffers correspond to:

X*SF_hor+OV_hor, and

Y*SF_ver+OV_ver

with SF being a scaling factor in the respective dimension, and OV being a measure of the computational overhead in the respective dimension corresponding to the number of lines and columns that are lost in the pipeline, and which is null for the horizontal dimension because of the translation of the scanning mode of said pair of first and second buffers when feeding pixel data to the pipeline.

14. A color image processing pipeline according to claim 10, wherein the given dimensions of the processed subset or block of pixels to be output by the pipeline are 16*16.

15. A method for reducing line memory without increasing overhead in a color image pixel data processing pipeline comprising:

interpolating chrominance data to generate triplets located at distinct pixel locations;

generating RGB information for each pixel of an input image pixel pattern using at least a first color interpolation block, and inputting the RGB information to a second color interpolation block for providing enhanced RGB pattern pixels, the first and second color interpolation blocks being part of a plurality of defect correction and image enhancement blocks;

permitting real-time processing of pixel data based upon a plurality of dedicated line memories and delay circuits associated with the plurality of defect correction and image enhancement blocks;

storing a subset or pixel block of the image data in first and second read/write buffers having an identical capacity; and

inverting a scanning mode of pixel data being fed to the plurality of dedicated line memories and delay circuits associated to at least the first color interpolation block, from row-wise to column-wise, for each subset of data to be stored therein.

16. A method according to claim 15, wherein for given dimensions of a processed subset or block of pixels to be output by the pipe line, the dimensions of the subset or pixel block of image data respectively written in and read from said first and second read/write buffers correspond to:

X*SF_hor+OV_hor, and

Y*SF_ver+OV_ver

with SF being a scaling factor in the respective dimension, and OV being a measure of the computational overhead in the respective dimension corresponding to the number of lines and columns that are lost in the pipeline and which is null for the horizontal dimension because of the translation of the scanning mode of said pair of first and second read/write buffers when feeding pixel data to the pipeline.

17. A method according to claim 15, wherein the given dimensions of the processed subset or block of pixels to be output by the pipeline are 16*16.

18. A method for processing color data comprising:

interpolating chrominance data to generate triplets located at distinct pixel locations;

generating RGB information for each pixel of an input image pixel pattern using at least a first color interpolation block, and inputting the RGB information to a second color interpolation block for providing enhanced RGB pattern pixels, the first and second color interpolation blocks being part of a plurality of defect correction and image enhancement blocks;

permitting real-time processing of pixel data based upon a plurality of dedicated line memories and delay circuits associated to and cooperating with the plurality of defect correction and image enhancement blocks;

storing a subset or pixel block of the image data in first and second buffers; and

inverting a scanning mode of pixel data being fed to the plurality of dedicated line memories and delay circuits associated to at least the first color interpolation block, from row-wise to column-wise, for each subset of data to be stored therein.

19. A method according to claim 18, wherein said first and second buffers comprise read/write buffers.

20. A method according to claim 18, wherein said first and second buffers are the same size.

21. A method according to claim 18, wherein for given dimensions of a processed subset or block of pixels to be output by the pipeline, the dimensions of the subset or pixel block of image data respectively written in and read from said first and second buffers correspond to:

X*SF_hor+OV_hor, and

Y*SF_ver+OV_ver

with SF being a scaling factor in the respective dimension, and OV being a measure of the computational overhead in the respective dimension corresponding to the number of lines and columns that are lost in the image processing pipeline, and which is null for the horizontal dimension because of the translation of the scanning mode of said pair of first and second buffers when feeding pixel data to the pipeline.

22. A method according to claim 18, wherein the given dimensions of the processed subset or block of pixels to be output by the pipeline are 16*16.