Information processing apparatus, information processing method, pattern recognition apparatus, and pattern recognition method

• US 20050283450A1
• Filed: 06/10/2005
• Published: 12/22/2005
• Est. Priority Date: 06/11/2004
• Status: Active Grant

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Mitarai, Yusuke, Matsugu, Masakazu, Mori, Katsuhiko, Ishii, Mie
• Granted Patent: US 7,676,441 B2
• Time in Patent Office: Days
• US Class Current: 706/20
• CPC Class Codes: G06N 3/049 Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
• CPC Class Codes: G06N 3/08 Learning methods
• CPC Class Codes: G06V 10/454 Integrating the filters into a hierarchical structure, e.g. convolutional neural networks [CNN]
• CPC Class Codes: G06V 40/19 Sensors therefor

Abstract

In a hierarchical neural network having a module structure, learning necessary for detection of a new feature class is executed by a processing module which has not finished learning yet and includes a plurality of neurons which should learn an unlearned feature class and have an undetermined receptor field structure by presenting a predetermined pattern to a data input layer. Thus, a feature class necessary for subject recognition can be learned automatically and efficiently.

Claims

1. An information processing apparatus which includes a data input layer and an arithmetic processing layer having at least one layer level and a plurality of processing modules corresponding to a plurality of feature classes to be detected and executes parallel hierarchical processing, said apparatus comprising:

at least one processing module which has finished learning, which includes a plurality of neurons having a receptor field structure used to detect a predetermined feature class in the arithmetic processing layer of at least one predetermined layer level; and

at least one processing module which has not finished learning yet, which includes a plurality of neurons which should learn an unlearned feature class and have an undetermined receptor field structure,

wherein learning necessary for detection of a new feature class is executed in said processing module which has not finished learning yet by presenting a predetermined pattern to the data input layer.

2. The apparatus according to claim 1, wherein the receptor field structure of the neurons included in said processing module which has finished learning is variable in a predetermined range in learning the new feature class.

3. The apparatus according to claim 1, wherein learning of the new feature class is executed at a plurality of layer levels.

4. The apparatus according to claim 1, wherein learning of a connection pattern necessary for detection of the new feature class is supervised learning to be executed for a processing module of a predetermined layer level higher than the layer where said processing module which has not finished learning yet is present, and a characteristic of a connection element between the arithmetic processing layers is determined.

5. The apparatus according to claim 4, wherein the learning of the connection pattern necessary for detection of the new feature class is self-organizing learning which decreases correlation between an operation element output of the added processing module and operation element outputs of remaining processing modules of the same layer level, which have finished learning.

6. The apparatus according to claim 5, wherein the self-organizing learning is learning based on the anti-Hebbian rule.

7. The apparatus according to claim 5, wherein at least one layer level of the arithmetic processing layer has an intralayer connection between the added processing module and said processing module which has finished learning, and the self-organizing learning executed in the layer to which the added processing module belongs is executed for an interlayer connection between the layer and a layer of a lower level and the intralayer connection.

8. The apparatus according to claim 4, wherein the learning of the connection pattern necessary for detection of the new feature class is self-organizing learning which is executed after supervised learning in the predetermined processing module of the upper layer to which the processing module to execute learning is connected converges.

9. The apparatus according to claim 4, wherein the learning of the connection pattern necessary for detection of the new feature class is self-organizing learning which decreases a mutual information amount related to an operation element output of the added processing module and operation element outputs of remaining processing modules of the same layer level, which have finished learning.

10. The apparatus according to claim 1, wherein the arithmetic processing layer is a convolutional neural network.

19. An image input apparatus which comprises an information processing apparatus according to claim 1.

11. An information processing apparatus which includes a data input layer, an arithmetic processing layer having at least one layer level and a plurality of processing modules corresponding to feature classes to be detected, a learning control circuit, and a processing module addition/deletion control circuit, said apparatus comprising:

determination means for determining whether an error signal of an operation element output at a predetermined layer level in the arithmetic processing layer satisfies a predetermined condition in a predetermined learning step executed by the learning control circuit; and

control means for, when said determination means determines that the predetermined condition is satisfied, executing control to cause the processing module addition/deletion control circuit to add at least one processing module in a layer of a level lower than the layer level.

12. The apparatus according to claim 11, wherein in the predetermined learning step, the learning control circuit sets a local initial connection between an operation element in the processing module added in the predetermined layer and an operation element in a predetermined processing module of a level lower than the layer, and the initial connection is formed with respect to an operation element of the lower layer which has a spatial layout different from a spatial layout of each operation element in the predetermined processing module of the lower layer to which the operation element in said processing module which has finished learning in the predetermined layer is connected.

13. The apparatus according to claim 11, wherein said control means causes the processing module addition/deletion control circuit to execute processing of adding a plurality of processing modules simultaneously, and a receptor field size of an operation element of the added processing module changes between the added processing modules.

14. The apparatus according to claim 11, wherein the processing module addition/deletion control circuit evaluates a relative degree of contribution of each processing module of a predetermined layer level in the arithmetic processing layer and deletes a processing module whose relative degree of contribution is smaller than a predetermined threshold value.

15. An information processing apparatus comprising:

an input layer which inputs predetermined input data;

independent component analysis means for executing independent component analysis for a predetermined data set;

learning control means;

an arithmetic processing layer which has at least one layer level and a plurality of processing modules corresponding to a plurality of feature classes to be detected; and

learning data setting means for setting learning input data containing a predetermined feature class to be learned by a predetermined processing module from the input data and a predetermined base data set obtained as a result of independent component analysis and storing the learning input data in a predetermined memory,

wherein said arithmetic processing layer of at least one predetermined layer level comprises

at least one processing module which has finished learning, which includes a plurality of neurons having a receptor field structure used to detect a predetermined feature class, and

at least one processing module which has not finished learning yet, which includes a plurality of neurons which should learn an unlearned feature class and have an undetermined receptor field structure, and

said learning control means executes learning necessary for detection of a new feature class in said processing module which has not finished learning yet by presenting the predetermined learning input data to a predetermined layer of said arithmetic processing layer.

16. The apparatus according to claim 15, wherein said learning data setting means extracts a prominent region of the base data set and sets, as the learning input data, data on the input data corresponding to the prominent region.

17. A pattern recognition apparatus comprising:

a data input layer;

an arithmetic processing layer which has at least one layer level and a plurality of processing modules corresponding to a plurality of feature classes to be detected;

learning control means; and

recognition result output means for outputting a predetermined pattern recognition result on the basis of an output from said arithmetic processing layer,

wherein said arithmetic processing layer of at least one predetermined layer level comprises

at least one processing module which has finished learning, which includes a plurality of neurons having a receptor field structure used to detect a predetermined feature class, and

at least one processing module which has not finished learning yet, which includes a plurality of neurons which should learn an unlearned feature class and have an undetermined receptor field structure, and

said learning control means executes learning necessary for detection of a new feature class in said processing module which has not finished learning yet by presenting a predetermined pattern to said data input layer.

20. An image input apparatus which comprises a pattern recognition apparatus according to claim 17.

18. A pattern recognition apparatus comprising:

a data input layer;

an arithmetic processing layer which has at least one layer level and a plurality of processing modules corresponding to a plurality of feature classes to be detected;

a learning control circuit;

a processing module addition/deletion control circuit; and

recognition result output means for outputting a predetermined pattern recognition result on the basis of an output from said arithmetic processing layer,

wherein when an error signal of an operation element output at a predetermined layer level in said arithmetic processing layer satisfies a predetermined condition in a predetermined learning step executed by said learning control circuit, said processing module addition/deletion control circuit adds at least one processing module in a layer of a level lower than the layer level.

21. An information processing method executed by an information processing apparatus which includes a data input layer, an arithmetic processing layer having at least one layer level and a plurality of processing modules corresponding to a plurality of feature classes to be detected, at least one processing module which has finished learning, which includes a plurality of neurons having a receptor field structure used to detect a predetermined feature class in the arithmetic processing layer of at least one predetermined layer level, and at least one processing module which has not finished learning yet, which includes a plurality of neurons which should learn an unlearned feature class and have an undetermined receptor field structure,

wherein learning necessary for detection of a new feature class is executed in the processing module which has not finished learning yet by presenting a predetermined pattern to the data input layer.

26. A program which causes a computer to execute an information processing method of claim 21.

22. An information processing method executed by an information processing apparatus which includes a data input layer, an arithmetic processing layer having at least one layer level and a plurality of processing modules corresponding to feature classes to be detected, a learning control circuit, and a processing module addition/deletion control circuit, said method comprising:

a determination step of determining whether an error signal of an operation element output at a predetermined layer level in the arithmetic processing layer satisfies a predetermined condition in a predetermined learning step executed by the learning control circuit; and

a control step of, when it is determined in the determination step that the predetermined condition is satisfied, executing control to cause the processing module addition/deletion control circuit to add at least one processing module in a layer of a level lower than the layer level.

23. An information processing method executed by an information processing apparatus which includes

an input layer which inputs predetermined input data,

independent component analysis means for executing independent component analysis for a predetermined data set,

learning control means,

an arithmetic processing layer which has at least one layer level and a plurality of processing modules corresponding to a plurality of feature classes to be detected, and

learning data setting means for setting learning input data containing a predetermined feature class to be learned by a predetermined processing module from the input data and a predetermined base data set obtained as a result of independent component analysis and storing the learning input data in a predetermined memory,

the arithmetic processing layer of at least one predetermined layer level including

at least one processing module which has finished learning, which includes a plurality of neurons having a receptor field structure used to detect a predetermined feature class, and

at least one processing module which has not finished learning yet, which includes a plurality of neurons which should learn an unlearned feature class and have an undetermined receptor field structure, wherein said learning control means executes learning necessary for detection of a new feature class in the processing module which has not finished learning yet by presenting the predetermined learning input data to a predetermined layer of the arithmetic processing layer.

24. A pattern recognition method executed by a pattern recognition apparatus including

a data input layer,

an arithmetic processing layer which has at least one layer level and a plurality of processing modules corresponding to a plurality of feature classes to be detected,

learning control means, and

recognition result output means for outputting a predetermined pattern recognition result on the basis of an output from the arithmetic processing layer,

the arithmetic processing layer of at least one predetermined layer level including

at least one processing module which has finished learning, which includes a plurality of neurons having a receptor field structure used to detect a predetermined feature class, and

at least one processing module which has not finished learning yet, which includes a plurality of neurons which should learn an unlearned feature class and have an undetermined receptor field structure, wherein

said learning control means executes learning necessary for detection of a new feature class in the processing module which has not finished learning yet by presenting a predetermined pattern to the data input layer.

27. A program which causes a computer to execute a pattern recognition method of claim 24.

25. A pattern recognition method executed by a pattern recognition apparatus including

a data input layer,

an arithmetic processing layer which has at least one layer level and a plurality of processing modules corresponding to a plurality of feature classes to be detected,

a learning control circuit,

a processing module addition/deletion control circuit, and

recognition result output means for outputting a predetermined pattern recognition result on the basis of an output from the arithmetic processing layer, wherein when an error signal of an operation element output at a predetermined layer level in the arithmetic processing layer satisfies a predetermined condition in a predetermined learning step executed by the learning control circuit, the processing module addition/deletion control circuit adds at least one processing module in a layer of a level lower than the layer level.

28. An information processing apparatus which executes processing of correcting a connection constant between layers to set, as a desired output value, an output value from each neuron included in a predetermined processing module in a predetermined detection layer in a hierarchical neural network which is constituted by alternately arranging, between a data input layer and a data output layer, a detection layer which includes a plurality of processing modules to detect a feature amount to be detected from an output from a layer of a preceding stage and an integration layer which integrates and outputs outputs from the detection layer, said apparatus comprising:

error calculation means for obtaining an error between the desired output value and the output value from each neuron included in the predetermined processing module in the predetermined detection layer;

addition means for adding a new processing module in accordance with the error in at least one layer of the layers arranged between the data input layer and the layer which outputs the output value to the predetermined processing module; and

correction means for, after addition processing by said addition means, correcting the connection constant between a predetermined number of layers from the predetermined detection layer to the data input layer on the basis of the error by said error calculation means.

29. An information processing method of executing processing of correcting a connection constant between layers to set, as a desired output value, an output value from each neuron included in a predetermined processing module in a predetermined detection layer in a hierarchical neural network which is constituted by alternately arranging, between a data input layer and a data output layer, a detection layer which includes a plurality of processing modules to detect a feature amount to be detected from an output from a layer of a preceding stage and an integration layer which integrates and outputs outputs from the detection layer, said method comprising:

an error calculation step of obtaining an error between the desired output value and the output value from each neuron included in the predetermined processing module in the predetermined detection layer;

an addition step of adding a new processing module in accordance with the error in at least one layer of the layers arranged between the data input layer and the layer which outputs the output value to the predetermined processing module; and

a correction step of, after addition processing in the addition step, correcting the connection constant between a predetermined number of layers from the predetermined detection layer to the data input layer on the basis of the error in the error calculation step.