Method and system for reducing latency in transferring captured image data

• US 20050283544A1
• Filed: 06/16/2004
• Published: 12/22/2005
• Est. Priority Date: 06/16/2004
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Yee, Dawson L.
• Granted Patent: US 7,254,665 B2
• Time in Patent Office: Days
• US Class Current: 710/35
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/0421 by interrupting or reflecting a light beam, e.g. optical touch-screen

Abstract

Video sensor data are communicated to a memory of a computer system with reduced latency. Upon receiving data from the video sensor, the data are stored until a desired transfer quantity is reached. The transfer quantity is equivalent to a width of a system memory or cache. When the number of data readings detected reaches an integer multiple of the transfer quantity, a bus request is issued. When the request is granted, the data readings are transferred to system memory in a burst mode. Because the transfer quantity is equivalent to a width of a system memory or cache, at least one line of memory or cache is filled during the course of the transfer. Thus, efficient use is made of bus resources. Also, because the processor can access a full line of system memory or cache without waiting for an additional fetch operation, processor resources are used efficiently.

Claims

1. A method for communicating information detected by a sensor to a system memory of a computer system over a bus, the method comprising the steps of:

(a) receiving successive data readings produced by a sensor, the sensor being disposed to monitor a condition in an area of interest;

(b) storing the data readings;

(c) tracking a number of data readings stored;

(d) requesting access to the bus when the number of data readings stored reaches a transfer quantity, the transfer quantity being equal to an integer multiple of one of a system cache width and a system memory width; and

(e) transferring the transfer quantity of data readings over the bus to the system memory in a burst mode, upon being granted access to the bus.

2. The method of claim 1, wherein the sensor includes a sensor array, the sensor array including a plurality of cells, each of which is responsive to an input signal including at least one of a visible spectrum light signal and a non-visible spectrum light signal and upon detecting the input signal, generates an analog signal representative of a magnitude of the input signal.

3. The method of claim 2, further comprising the step of converting analog signals from the sensor to digital signals such that magnitudes of each of the analog signals generated by cells within the sensor array are digitized to produce the data readings, values of the data readings being representative of the magnitudes of the analog signals.

4. The method of claim 1, wherein for each of the data readings, further comprising the step of producing and transferring at least one additional signal over the bus, the additional signal providing identifying information about a nature of the data reading.

5. The method of claim 4, wherein the additional signal includes a timing signal indicating an end of a frame.

6. The method of claim 1, wherein the data readings are stored in a storage area having a storage capacity equivalent to a multiple of the transfer quantity.

7. The method of claim 6, wherein the storage area includes a primary storage area and a secondary storage area, and the data readings are directed to the secondary storage area when the primary storage area stores at least a multiple of one times the transfer quantity of storage bytes.

8. The method of claim 1, wherein the bus is one of a peripheral component interface bus, a peripheral component interface express bus, and an accelerated graphics port bus.

9. The method of claim 1, wherein the transfer quantity is established such that the data readings for the area of interest consist of an integer number of transfer quantities.

10. The method of claim 1, further comprising the step of generating a processor interrupt after transferring a plurality of transfer quantities of data readings corresponding to a set of data readings for all of the area of interest.

11. A method for communicating information to a system memory of a computer system over a bus, the method comprising the steps of:

(a) receiving a plurality of input signals at each of a plurality of cells in a sensor array, the sensor array being positioned to monitor an area of interest;

(b) generating analog output signals for each of the plurality of cells, a magnitudes of each of the analog output signals representing a magnitude of each of the plurality of input signals;

(c) digitizing each of the plurality of analog output signals into a plurality of data readings, a value of each of the plurality of data readings being representative of the magnitude of each of the plurality of analog output signals;

(d) storing the data readings in a storage area;

(e) tracking a number of the data readings stored;

(f) requesting access to the bus when the number of data readings stored reaches a transfer quantity, the transfer quantity being equal to an integer multiple of a system cache width; and

(g) transferring the transfer quantity of data readings over the bus to the system memory in a burst mode upon being granted access to the bus.

12. The method of claim 11, wherein the sensor array comprises an array of sensors responsive to at least one of visible spectrum light signals and non-visible spectrum light signals.

13. The method of claim 11, wherein for each of the data readings, further comprising the step of receiving at least one additional signal, the additional signal providing identifying information about a nature of the data readings.

14. The method of claim 13, wherein the additional signal includes a timing signal indicating an end of a frame.

15. The method of claim 11, wherein the data readings are stored in a storage area comprising a system cache.

16. The method of claim 11, wherein the storage area includes a primary storage area and a secondary storage area, and the data readings are directed to the secondary storage area when the primary storage area stores at least an integer multiple of the transfer quantity of storage bytes.

17. The method of claim 11, wherein the bus is one of a peripheral component interface bus, a peripheral component interface express bus, and an accelerated graphics port bus.

18. The method of claim 11, wherein the transfer quantity is established such that the data readings for the area of interest comprise an integer number of transfer quantities.

19. The method of claim 11, further comprising the step of generating a processor interrupt after transferring a plurality of transfer quantities of data readings such that the plurality of transfer quantities represents a set of data for all of the area of interest.

20. A system for communicating information from a sensor to a system memory of a computer system over a bus, the system comprising:

(a) a sensor input configured to receive data readings generated by the sensor;

(b) a storage buffer configured to store a plurality of data readings received via the sensor input;

(c) a counter configured to count a number of data readings received via the sensor input;

(d) a bus interface coupled to the bus and to the storage buffer, the bus interface being configured to selectively transfer data readings from the storage buffer over the bus; and

(e) a controller in communication with the counter, the storage buffer, and the bus interface, the controller executing instructions for carrying out a plurality of functions, including;

(i) causing a bus access request to be generated when the number of data readings received for storage in the storage buffer reaches a transfer quantity, the transfer quantity being defined in regard to one of a system cache width and a system memory width; and

(ii) causing the transfer quantity of data readings to be transferred from the storage buffer over the bus to the system memory in a burst mode, upon the bus interface being granted access to the bus.

21. The system of claim 20, wherein the sensor includes a sensor array, the sensor array including a plurality of cells each of which is responsive to an input signal comprising at least one of a visible spectrum light signal and a non-visible spectrum light signal, and upon detecting the input signal, generates an analog signal representative of a magnitude of the input signal.

22. The system of claim 21, further comprising an analog-to-digital converter configured to convert analog signals generated by the cells of the sensory array to the data readings, a value of each of the data readings being representative of a magnitude of the analog signal.

23. The system of claim 20, wherein each of the data readings is associated with at least one additional signal, the additional signal providing identifying information about a nature of the data readings.

24. The system of claim 23, wherein the additional signal includes a timing signal indicating an end of a frame.

25. The system of claim 20, wherein storage buffer includes a storage capacity equivalent to an integer multiple of the transfer quantity.

26. The system of claim 20, wherein the storage buffer includes a primary buffer and a secondary buffer, and the data readings are directed to the secondary buffer when the primary buffer stores at least a multiple of one times the transfer quantity, of data readings.

27. The system of claim 26, further comprising a switch operatively coupled with the controller, the switch being configured to selectively direct the data readings to one of the primary buffer and the secondary buffer.

28. The system of claim 20, wherein the counter includes one of a counter configured to monitor a number of data readings received from the sensor and a status flag, the status flag indicating that the transfer quantity has been reached when the storage buffer is storing an integer multiple of the transfer quantity.

29. The system of claim 20, wherein the bus comprises one of a peripheral component interface bus, a peripheral component interface express bus, and an accelerated graphics port bus.

30. The system of claim 20, wherein the transfer quantity is established such that the area of interest includes an integer number of transfer quantities.

31. The system of claim 20, further comprising a processor interrupt generator coupled with the controller, the processor interrupt generator being configured to generate a processor interrupt after a plurality of transfer quantities of data readings has been transferred to the data bus such that the plurality of transfer quantities represents a set of data for all of the area of interest.

32. A system for communicating information to a system memory of a computer system over a bus, comprising:

(a) a sensor array, the sensor array including a plurality of cells, each of which is responsive to an input signal including at least one of a visible spectrum light signal and a non-visible spectrum light signal, wherein upon detecting the input signal, each of the cells generates an analog signal representative of a magnitude of the input signal at the cell;

(b) an analog-to-digital converter configured to convert analog signals generated by the cells of the sensory array into data readings, a value of each of the data readings being representative of the magnitude of the analog signal;

(c) a storage buffer configured to store a plurality of data readings;

(d) a counting system configured to count a number of data readings received from the sensor array;

(e) a bus interface coupled to the bus and to the storage buffer, the bus interface being configured to selectively transfer data readings from the storage buffer to the system memory over the bus; and

(f) a controller in communication with the counting system, the storage buffer, and the bus interface, the controller storing instructions that cause the controller to carry out a plurality of functions, including;

(i) causing a bus access request to be generated when the number of data readings stored reaches a transfer quantity, the transfer quantity being equal to an integer multiple of one of a system cache width and a system memory width; and

(ii) causing the transfer quantity of data readings to be transferred from the storage buffer to the system memory over the bus in a burst mode upon the bus interface being granted access to the bus.

33. The system of claim 32, wherein each of the data readings is associated with at least one additional signal, the additional signal providing identifying information about a nature of each of the data readings.

34. The system of claim 33, wherein the additional signal includes a timing signal indicating an end of a frame.

35. The system of claim 32, wherein storage buffer includes a storage capacity equivalent to an integer multiple of the transfer quantity.

36. The system of claim 32, wherein the storage buffer includes a primary buffer and a secondary buffer, and wherein the data readings are directed to the secondary buffer when the primary buffer stores at least a multiple one times the transfer quantity of data readings.

37. The system of claim 36, further comprising a switch operatively coupled with the controller, the switch being configured to direct the data readings to one of the primary buffer and the secondary buffer.

38. The system of claim 32, wherein the counting system includes one of a counter configured to monitor a number of data readings received from the sensor and a status flag, the status flag being indicating that the transfer quantity is reached when the storage buffer stores an integer multiple of the transfer quantity.

39. The system of claim 32, wherein the bus comprises one of a peripheral component interface bus, a peripheral component interface express bus, and an accelerated graphics port bus.

40. The system of claim 32, wherein the transfer quantity is established such that data readings for the area of interest includes an integer number of transfer quantities.

41. The system of claim 32, further comprising a processor interrupt generator coupled with the controller, the processor interrupt generator being configured to generate a processor interrupt after a plurality of transfer quantities of data readings has been transferred to the data bus such that the plurality of transfer quantities represents a set of data representing all of the area of interest.

42. A system for providing an input to an application that is being executed, comprising:

(a) an interactive display surface adjacent to which a physical object is manipulated, said interactive display surface diffusing light, and having a processing side and an interactive side from which the image is viewed and adjacent to which the physical object can be placed, the processing side being opposite to the interactive side;

(b) a projector that projects graphic images onto the processing side of the interactive display surface, said graphic images being visible from the interactive side;

(c) a light source disposed on the processing side of the display surface, the light source emitting infrared light that is transmitted through the display surface to the interactive side and reflected back through the interactive display surface by the physical object that is disposed adjacent to the interactive side of the interactive display surface;

(d) a light sensor disposed on the processing side of the interactive display surface, the light sensor producing an analog signal upon sensing infrared light reflected back from the physical object through the interactive display surface;

(e) an analog-to-digital converter configured to convert the analog signal into data readings, a value of each the data readings being representative of a magnitude of the analog signal;

(f) a processor in communication with a bus;

(g) a memory in communication with the processor over the bus, the memory, the memory storing data and machine instructions that cause the processor to carry out a plurality of functions in response to the analog signal; and

(h) a data interface operatively coupled with the analog-to-digital converter and the bus to communicate the data readings to the memory over the bus, the data interface including;

(i) a data input configured to receive the input generated by the light sensor;

(ii) a storage buffer configured to store a plurality of data readings received via the data input;

(iii) a counting system configured to count a number of data readings received via the data input;

(iv) a bus interface coupled to the bus and the storage buffer, the bus interface being configured to selectively transfer data readings from the storage buffer to the memory over the bus; and

(v) a controller in communication with the counting system, the storage buffer, and the bus interface, the controller executing instructions that cause the controller to carry out a plurality of functions, including;

(A) causing a bus access request to be generated when the number of data readings stored in the storage buffer reaches a transfer quantity, the transfer quantity being determined in respect to one of a system cache width and a system memory width; and

(B) causing the transfer quantity of data readings to be transferred from the storage buffer to memory over the bus in a burst mode, upon the bus interface being granted access to the bus.

43. The system of claim 42, wherein each of the data readings is associated with at least one additional signal, the additional signal providing identifying information about a nature of each of the data readings.

44. The system of claim 43, wherein the additional signal includes a timing signal indicating an end of a frame.

45. The system of claim 42, wherein the storage buffer includes a storage capacity equivalent to an integer multiple of the transfer quantity.

46. The system of claim 42, wherein the storage buffer includes a primary buffer and a secondary buffer, and the data readings are directed to the secondary buffer when the primary buffer is storing at least a multiple of one time the transfer quantity of data readings.

47. The system of claim 46, further comprising a switch operatively coupled with the controller, the switch being configured to direct the data readings to one of the primary buffer and the secondary buffer.

48. The system of claim 42, wherein the counting system includes one of a counter configured to monitor a number of data readings received from the sensor and a status flag, the status flag being configured to indicate the transfer quantity is reached when the storage buffer is storing an integer multiple of the transfer quantity.

49. The system of claim 42, wherein the bus is one of a peripheral component interface bus, a peripheral component interface express bus, and an accelerated graphics port bus.

50. The system of claim 42, wherein the transfer quantity is established such that the data readings for the area of interest comprise an integer number of transfer quantities.

51. The system of claim 42, further comprising a processor interrupt generator coupled with the controller, the processor interrupt generator being configured to generate a processor interrupt after a plurality of transfer quantities of data readings has been transferred to the data bus such that the plurality of transfer quantities represents a set of data readings for all of the area of interest.