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Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers

  • US 20050283546A1
  • Filed: 08/15/2005
  • Published: 12/22/2005
  • Est. Priority Date: 12/17/1997
  • Status: Active Grant
First Claim
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1. A computer system comprising:

  • at least one processor including memory mapped registers mapped into the address space of the at least one processor;

    a controller for coupling said at least one processor to a control block and a memory bus;

    a plurality of memory module slots coupled to said memory bus;

    an adapter port associated with a subset of said plurality of memory module slots; and

    a processor element coupled to said adapter port, wherein polling of the memory mapped registers by the at least one processor provides a direct low latency communication link between the processor and the processor element for communicating DMA requests.

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