Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers
First Claim
1. A computer system comprising:
- at least one processor including memory mapped registers mapped into the address space of the at least one processor;
a controller for coupling said at least one processor to a control block and a memory bus;
a plurality of memory module slots coupled to said memory bus;
an adapter port associated with a subset of said plurality of memory module slots; and
a processor element coupled to said adapter port, wherein polling of the memory mapped registers by the at least one processor provides a direct low latency communication link between the processor and the processor element for communicating DMA requests.
9 Assignments
0 Petitions
Accused Products
Abstract
A switch/network adapter port (“SNAP™”) in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format for clustered computers employing multi-adaptive processor (“MAP®”, both trademarks of SRC Computers, Inc.) elements for use with interleaved memory controllers. Particularly disclosed is a microprocessor based computer system utilizing either a DIMM or RIMM physical format adapter port coupled to a reconfigurable processor element for the purpose of implementing a connection to an external switch, network, or other device. In a particular embodiment, connections may be provided to either the PCI, accelerated graphics port (“AGP”) or system maintenance (“SM”) bus for purposes of passing control information to the host microprocessor or other control chips. The field programmable gate array (“FPGA”) based processing elements have the capability to alter data passing through it to and from an external interconnect fabric or device.
-
Citations
25 Claims
-
1. A computer system comprising:
-
at least one processor including memory mapped registers mapped into the address space of the at least one processor;
a controller for coupling said at least one processor to a control block and a memory bus;
a plurality of memory module slots coupled to said memory bus;
an adapter port associated with a subset of said plurality of memory module slots; and
a processor element coupled to said adapter port, wherein polling of the memory mapped registers by the at least one processor provides a direct low latency communication link between the processor and the processor element for communicating DMA requests. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
-
-
25. A method of operating a computer system comprising:
-
providing at least one processor including memory mapped registers mapped into the address space of the at least one processor;
coupling said at least one processor to a control block and a memory bus;
providing a plurality of memory module slots coupled to said memory bus;
providing an adapter port associated with a subset of said plurality of memory module slots;
providing a processor element coupled to said adapter port; and
polling the memory mapped registers by the at least one processor to provide a direct low latency communication link between the processor and the processor element for communicating DMA requests.
-
Specification