Method and architecture of a coupling system for microprocessors and logic devices

• US 20050283550A1
• Filed: 06/18/2004
• Published: 12/22/2005
• Est. Priority Date: 06/18/2004
• Status: Abandoned Application

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Ramos, Jeremy
• Application Number:
  US10/872,216
• Publication Number:
  US 20050283550A1
• Time in Patent Office: Days
• US Class Current: 710/62
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox

Abstract

A system for coupling processors and logic devices is provided. The system includes a central processing unit node and a re-configurable computing node that are coupled to a shared memory. The system further includes a discrete I/O bus used for signaling between the central processing unit node and the re-configurable computing node.

Claims

1. A system comprising:

a processor;

a logic device;

a shared memory; and

wherein the processor is coupled to the logic device through the shared memory to pass data and results between the processor and the logic device.

2. The system of claim 1, wherein the processor and the logic device are radiation hardened.

3. The system of claim 1, wherein the shared memory is radiation hardened.

4. The system of claim 1, wherein the shared memory is a dual port memory with a first port coupled to the processor and the second port coupled to the logic device.

5. The system of claim 1, wherein the logic device is a field programmable gate array.

6. The system of claim 5, wherein the field programmable gate array has an operating system that is hardware implemented.

7. A method for communicating data between a processor and a logic device in an electronic system, said method comprising:

generating data at the processor;

providing the data from the processor to a first port of a shared memory;

reading the data from a second port of the shared memory into the logic device; and

processing the data at the logic device.

8. The method in claim 7, wherein processing the data at the logic device comprises processing the data at a field programmable gate array.

9. The method of claim 7, wherein generating data in the processor comprises generating data in a radiation hardened processor;

and

processing the data at the logic device comprises processing data in a radiation hardened logic device.

12. The method of claim 7, wherein generating the results in the processor comprises processing the results in a radiation hardened processor;

and

processing the data in the logic device comprises processing data in a radiation hardened logic device.

10. A method for communicating data between a logic device and a processor in an electronic system, said method comprising:

processing data in a logic device;

generating results at the logic device;

providing the results from the logic device to a first port of a shared memory;

reading results from a second port of the shared memory into the processor; and

processing the results at the processor.

11. The method in claim 10, wherein processing the data in the logic device comprises processing the data in a field programmable gate array.

13. A system for coupling processors and logic devices comprising:

a central processing unit node;

a re-configurable computing node;

a discrete I/O bus; and

wherein the central processing unit node and the re-configurable computing node are directly coupled to a shared memory.

14. The system of claim 13, wherein the central processing unit includes a processor and a system controller.

15. The system of claim 13, wherein the re-configurable computing node includes a shared memory and a logic device.

16. The system of claim 13, wherein the central processing unit node is radiation hardened.

17. The system of claim 13, wherein the re-configurable computing node is radiation hardened.

18. The system of claim 13, wherein the discrete I/O bus provides signaling between the central processing unit node and the re-configurable computing node.

19. A method for communicating data between a central processing unit node and a re-configurable computing node in an electronic system, said method comprising:

generating data at the central processing unit node;

providing the data from the central processing unit to a shared memory;

reading the data from the shared memory into the re-configurable computing node; and

processing the data at the re-configurable computing node.

20. The method of claim 19, wherein reading data from the shared memory comprises reading data substantially simultaneously as the data is provided to the shared memory by the central processing node.

21. The method of claim 19, wherein reading the data from a shared memory comprises reading the data from a dual port memory.

22. The method of claim 19, and further comprising providing results back to the re-configurable computing node through the shared memory.

23. The method of claim 19, wherein generating data at the central processing unit node comprises generating data at a radiation hardened central processing unit node.

24. The method of claim 19, wherein processing the data at the re-configurable computing node comprises processing the data at the re-configurable computing node with a radiation hardened logic device.

25. A system for connecting logic devices comprising:

a first logic device;

a second logic device;

a shared memory; and

wherein the first logic device is directly coupled to the second logic device using the shared memory.

26. The system of claim 25, wherein the first logic device is a field programmable gate array.

27. The system of claim 25, wherein the field programmable gate array has an operating system that is hardware implemented.

28. The system of claim 25, wherein the second logic device is an analog-digital converter.

29. The system in claim 25, wherein the second logic device is a digital-analog converter.

30. The system in claim 25, wherein the shared memory is a dual port memory.

31. A method for processing data, the method comprising:

processing first data in a processor based on stored instructions;

processing other data in a logic device based on a hardware configuration of the logic device; and

passing data and results between the processor and logic device using a shared memory that is directly accessible by both processor and the logic device.