Mechanism to handle events in a machine with isolated execution

• US 20050283660A1
• Filed: 07/21/2005
• Published: 12/22/2005
• Est. Priority Date: 09/28/2000
• Status: Abandoned Application

• Current Assignee: Benjamin Crawford Chaffin, Bryant Bigbee, Francis X. Mckeen, Lawrence O. Smith, Michael P. Cornaby
• Original Assignee: Benjamin Crawford Chaffin, Bryant Bigbee, Francis X. Mckeen, Lawrence O. Smith, Michael P. Cornaby
• Inventors: Bigbee, Bryant, Smith, Lawrence O., McKeen, Francis X., Chaffin, Benjamin Crawford, Cornaby, Michael P.
• Application Number:
  US11/187,731
• Publication Number:
  US 20050283660A1
• Time in Patent Office: Days
• US Class Current: 714/11
• CPC Class Codes: G06F 12/145 the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism
• CPC Class Codes: G06F 12/1491 in a hierarchical protection system, e.g. privilege levels, memory rings
• CPC Class Codes: G06F 21/52 during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
• CPC Class Codes: G06F 21/53 by executing in a restricted environment, e.g. sandbox or secure virtual machine
• CPC Class Codes: G06F 21/74 operating in dual or compartmented mode, i.e. at least one secure mode

Abstract

A platform and method for secure handling of events in an isolated execution environment. A processor executing in isolated execution “IsoX” mode may leak data when an event occurs as a result of the event being handled in a traditional manner based on the exception vector. By defining a class of events to be handled in IsoX mode, and switching between a normal memory map and an IsoX memory map dynamically in response to receipt of an event of the class, data security may be maintained in the face of such events.

Claims

1. A method comprising:

distinguishing between at least two execution modes of a central processing unit in an information processing system;

maintaining at least two sets of processor control registers within the central processing unit;

recognizing an asynchronous event;

determining which execution mode is desired for responding to the asynchronous event; and

if the current execution mode is not the same as the desired execution mode for responding to the asynchronous event, altering the current execution mode to the desired execution mode before responding to the asynchronous event, wherein

at least one set of processor control registers is inaccessible to the processor in at least one of the execution modes.

2. The method of claim 1 wherein the at least two sets of processor control registers comprise virtual memory management registers.

3. The method of claim 1 wherein the at least two sets of processor control registers comprise interrupt vector table registers.

4. The method of claim 1 wherein the asynchronous event is a machine check event.

5. The method of claim 1 wherein the asynchronous event is a clock interrupt.

6. The method of claim 1 wherein the asynchronous event is a hardware interrupt.

7. An apparatus comprising:

a central processing unit (CPU) capable of operating in one of at least two execution modes;

a storage location that identifies a current execution mode of the CPU;

a plurality of resources operatively joined to the CPU; and

a mechanism to restrict access to a subset of the plurality of resources based on the current execution mode of the CPU.

8. The apparatus of claim 7 wherein the mechanism to restrict access to a subset of the plurality of resources comprises a signal provided by the CPU that indicates whether the current execution mode permits access to the plurality of resources.

9. The apparatus of claim 7 wherein the resource to which access is restricted is a special-purpose control register.

10. The apparatus of claim 9 wherein the special purpose control register is a virtual memory management descriptor.

11. The apparatus of claim 9 wherein the special purpose control register is an interrupt vector table descriptor.

12. The apparatus of claim 7 wherein the resource to which access is restricted is a device located outside the CPU.

13. The apparatus of claim 7 wherein the resource to which access is restricted is a random-access memory location.

14. A method of preventing inadvertent disclosure of information contained within a CPU comprising:

distinguishing between a normal and an isolated execution mode;

maintaining a separate set of control registers that are only accessible when the CPU is operating in the isolated execution mode;

defining a set of events that should be handled in the isolated execution mode;

determining if an event is a member of the set of events when the event occurs; and

if the event is a member of the set of events and the CPU is operating in the normal execution mode, switching to the isolated execution mode before executing instructions in response to said event.

15. The method of claim 14 wherein the set of events comprises machine check exceptions and clock events.