Duration minimum and maximum circuit for performance counter

• US 20050283677A1
• Filed: 12/23/2004
• Published: 12/22/2005
• Est. Priority Date: 06/03/2004
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Adkisson, Richard W., Johnson, Tyler
• Granted Patent: US 7,676,530 B2
• Time in Patent Office: Days
• US Class Current: 714/38.1
• CPC Class Codes: G06F 11/348 Circuit details, i.e. tracer hardware
• CPC Class Codes: G06F 2201/88 Monitoring involving counting

Abstract

A circuit for tracking the minimum and maximum duration of an event of interest is described. The circuit is connected to a counter for counting a number of clock cycles that the event of interest is active and comprises logic for detecting deactivation of the event of interest and generating a duration end signal; logic responsive to the duration end signal for comparing a count value with a shadow value; and logic for updating the shadow value based on results of the comparing.

Claims

1. A circuit for tracking the minimum and maximum duration of an event of interest, the circuit connected to a counter for counting a number of clock cycles that the event of interest is active, the circuit comprising:

logic for detecting deactivation of the event of interest and generating a duration end signal;

logic responsive to the duration end signal for comparing a count value with a shadow value; and

logic for updating the shadow value based on results of the comparing.

2. The circuit of claim 1 further comprising logic for selecting a mode of operation of the circuit.

3. The circuit of claim 2 wherein when a minimum mode of operation is selected, the logic for comparing activates a less than signal responsive to the count value being less than the shadow value.

4. The circuit of claim 3 wherein the logic for updating comprises logic for replacing the shadow value with the count value responsive to activation of the less than signal.

5. The circuit of claim 2 wherein when a maximum mode of operation is selected, the logic for comparing activates a greater than signal responsive to the count value being greater than the shadow value.

6. The circuit of claim 5 wherein the logic for updating further comprises logic for replacing the shadow value with the count value responsive to activation of the greater than signal.

7. The circuit of claim 1 further comprising a count register for storing the count value.

8. The circuit of claim 1 further comprising a shadow register for storing the shadow value.

9. The circuit of claim 1 further comprising logic for detecting a valid clock cycle.

10. The circuit of claim 9 further comprising logic for preventing activation of the duration end signal unless a valid clock cycle is detected.

11. A circuit for tracking the minimum and maximum duration of an event of interest, the circuit connected to a counter for counting a number of clock cycles that the event of interest is active, the circuit comprising:

means for detecting deactivation of the event of interest and generating a duration end signal;

means responsive to the duration end signal for comparing a count value with a shadow value; and

means for updating the shadow value based on results of the comparing.

12. The circuit of claim 11 further comprising means for selecting a mode of operation of the circuit.

13. The circuit of claim 12 wherein when a minimum mode of operation is selected, the means for comparing activates a less than signal responsive to the count value being less than the shadow value.

14. The circuit of claim 13 wherein the means for updating comprises means for replacing the shadow value with the count value responsive to activation of the less than signal.

15. The circuit of claim 12 wherein when a maximum mode of operation is selected, the means for comparing activates a greater than signal responsive to the count value being greater than the shadow value.

16. The circuit of claim 15 wherein the means for updating further comprises means for replacing the shadow value with the count value responsive to activation of the greater than signal.

17. The circuit of claim 11 further comprising a count register for storing the count value.

18. The circuit of claim 11 further comprising a shadow register for storing the shadow value.

19. The circuit of claim 11 further comprising means for detecting a valid clock cycle.

20. The circuit of claim 19 further comprising means for preventing activation of the duration end signal unless a valid clock cycle is detected.

21. A method of tracking the minimum and maximum duration of an event of interest using a circuit connected to a counter for counting a number of clock cycles that the event of interest is active, the method comprising:

detecting deactivation of the event of interest and generating a duration end signal;

responsive to the duration end signal, comparing a count value with a shadow value; and

updating the shadow value based on results of the comparing.

22. The method of claim 21 further comprising selecting a mode of operation of the circuit.

23. The method of claim 22 comprising activating a less than signal responsive to the count value being less than the shadow value when a minimum mode of operation is selected.

24. The method of claim 23 wherein the updating comprises replacing the shadow value with the count value responsive to activation of the less than signal.

25. The method of claim 22 wherein the comparing activates a greater than signal responsive to the count value being greater than the shadow value when a maximum mode of operation is selected.

26. The method of claim 25 wherein the updating further comprises replacing the shadow value with the count value responsive to activation of the greater than signal.

27. The method of claim 21 further comprising detecting a valid clock cycle.

28. The method of claim 27 further comprising preventing activation of the duration end signal unless a valid clock cycle is detected.