Semiconductor test apparatus for simultaneously testing plurality of semiconductor devices

• US 20050283697A1
• Filed: 06/15/2005
• Published: 12/22/2005
• Est. Priority Date: 06/18/2004
• Status: Active Grant

• Current Assignee: UniTest Inc.
• Original Assignee: UniTest Inc.
• Inventors: Kang, Jong Koo, Kim, Sun Whan
• Granted Patent: US 7,607,056 B2
• Time in Patent Office: Days
• US Class Current: 714/742
• CPC Class Codes: G01R 31/31932 Comparators
• CPC Class Codes: G06F 11/263 Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers

Abstract

Disclosed herein is a semiconductor test apparatus for simultaneously testing a plurality of semiconductor devices. The semiconductor test apparatus includes a plurality of pattern generation boards, a DUT board, a backplane board, and a power supply unit. The pattern generation boards receive a test program, generate a test pattern signal and an expected signal, transmit the test pattern signal to the semiconductor devices, receive a test pattern result signal, compare the test pattern result signal with the expected signal, generate a Direct Current (DC) test signal and a DC test expected signal, transmit the DC test signal to the semiconductor devices, receive a DC test result signal and compare the DC test result signal with the DC test expected signal. The DUT board includes a plurality of sockets for connection to the semiconductor devices and a plurality of connectors for connection to the pattern generation boards. The DUT board receives the test pattern signal or the DC test signal, transmits the received signal to the semiconductor devices, receives the test pattern result signal or DC test result signal and transmits the received signal to the pattern generation boards. The backplane board includes a plurality of connectors for connection to the plurality of pattern generation boards and a communication interface unit, and mechanically supports the pattern generation boards. The power supply unit mechanically supports the backplane board and supplies power to the backplane board.

Claims

1. A semiconductor test apparatus for simultaneously testing a plurality of semiconductor devices, comprising:

a plurality of pattern generation boards for receiving a test program from an external server, generating a test pattern signal and an expected signal, transmitting the test pattern signal to the semiconductor devices, receiving a test pattern result signal from the semiconductor devices, comparing the test pattern result signal with the expected signal, generating a Direct Current (DC) test signal and a DC test expected signal for a DC test, transmitting the DC test signal to the semiconductor devices, and receiving a DC test result signal from the semiconductor devices, comparing the DC test result signal with the DC test expected signal;

a Device Under Test (DUT) board including a plurality of sockets for connection to the semiconductor devices and a plurality of connectors for connection to the pattern generation boards, the DUT board receiving the test pattern signal or the DC test signal from the pattern generation boards, transmitting the test pattern signal or DC test signal to the semiconductor devices, receiving the test pattern result signal or DC test result signal from the semiconductor devices, and transmitting the test pattern result signal or DC test result signal to the pattern generation boards;

a backplane board including a plurality of connectors for connection to the plurality of pattern generation boards, the backplane board mechanically supporting the pattern generation boards, the backplane board including a communication interface unit for connection to the external server; and

a power supply unit for mechanically supporting the backplane board and supplying power to the backplane board.

2. The semiconductor test apparatus according to claim 1, wherein each of the pattern generation boards comprises:

a programmable device for receiving the test program, generating the test pattern signal and the expected signal, transmitting the test pattern signal to a corresponding semiconductor device, receiving the test pattern result signal from the semiconductor device, and comparing the test pattern result signal with the expected signal, thus testing operation of the semiconductor device;

a power measurement unit for generating the DC test signal and the DC test expected signal to perform the DC test, transmitting the DC test signal to the semiconductor device, receiving the DC test result signal from the semiconductor device and performing comparison with the DC test expected signal;

a DUT interface unit including a test pattern interface that transmits the test pattern signal to the semiconductor device while minimizing signal distortion, receives the test pattern result signal from the semiconductor device and transmits the test pattern result signal to the programmable device, a power interface that transmits the DC test signal to the semiconductor device, receives the DC test result signal from the semiconductor device and transmits the DC test result signal to the power measurement unit, and a termination interface that performs termination;

a clock generator for generating a clock and providing the clock to the programmable device;

a Phase Locked Loop (PLL) for transmitting a clock signal having the same phase to the DUT interface unit;

a backplane interface unit for providing an interface with the backplane board to communicate with the external server and to be supplied with power from the power supply unit; and

a control unit for controlling operation of the programmable device, the power measurement unit, the DUT interface unit, the clock generator, the PLL and the backplane interface unit.

3. The semiconductor test apparatus according to claim 2, wherein the control unit performs control so that the power interface of the DUT interface unit is set to be ON and the test pattern interface and the termination interface are set to be OFF when the DC test is performed, and the power interface of the DUT interface unit is set to be OFF and the test pattern interface and the termination interface are set to be ON when a function test is performed.

4. The semiconductor test apparatus according to claim 1, wherein the communication interface unit is an interface satisfying a Peripheral Component Interconnect (PCI) communication standard.

5. The semiconductor test apparatus according to claim 1, wherein the power supply unit comprises:

a plurality of programmable power supply units for supplying power having a plurality of voltages;

a power board for controlling supply of power to the programmable power supply units; and

a DC power source for supplying DC power to the power board.

6. The semiconductor test apparatus according to claim 1, wherein the DUT board comprises a plurality of sockets in which semiconductor modules are mounted, the semiconductor devices are the semiconductor modules, and the plurality of connectors of the DUT board for connection to the pattern generation boards interfaces the pattern generation boards with the sockets, in which the semiconductor modules are mounted and which correspond to respective pattern generation boards, to transmit/receive signals.

7. The semiconductor test apparatus according to claim 1, wherein the DUT board comprises a plurality of sockets in which semiconductor components are mounted, the semiconductor devices are the semiconductor components, and the plurality of connectors of the DUT board for connection to the pattern generation boards interfaces the pattern generation boards with semiconductor components designated with respect to the pattern generation boards through cable connections to transmit/receive signals.

8. The semiconductor test apparatus according to any of claims 1 to 7, wherein the programmable device is a Field Programmable Gate Array (FPGA) in which a function of generating the test pattern signal and the expected signal, a function of comparing the test pattern result signal with the expected signal, and a function of inputting the test pattern signal to the semiconductor devices are implemented on one chip.