Thin film transistor and method of fabricating the same

• US 20050285197A1
• Filed: 06/27/2005
• Published: 12/29/2005
• Est. Priority Date: 06/29/2004
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Park, Byoung-Keon
• Granted Patent: US 9,070,716 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02595 polycrystalline
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H10K 59/12 Active-matrix OLED [AMOLED] displays

Abstract

A thin film transistor including a substrate having first and second regions, a semiconductor layer pattern formed in the first region and the second region, and a first gate insulating layer pattern formed on a channel region of the semiconductor layer pattern of the first region. A second gate insulating layer is formed on the substrate, a first conductive layer pattern is formed above the channel region of the first region and above the semiconductor layer pattern of the second region, and an inter-layer insulating layer is formed on the substrate. A second conductive layer pattern is formed in the first region and above the first conductive layer pattern of the second region. The second conductive layer pattern of the first region is coupled to the semiconductor layer pattern of the first region through the second gate insulating layer and the inter-layer insulating layer.

Claims

1. A thin film transistor, comprising:

a substrate having a first region and a second region;

a semiconductor layer pattern formed in the first region and the second region;

a first gate insulating layer pattern formed on a channel region of the semiconductor layer pattern of the first region;

a second gate insulating layer formed on the substrate;

a first conductive layer pattern formed above the channel region of the first region and above the semiconductor layer pattern of the second region;

an inter-layer insulating layer formed on the substrate; and

a second conductive layer pattern formed in the first region and above the first conductive layer pattern of the second region,

wherein the second conductive layer pattern of the first region is coupled to the semiconductor layer pattern of the first region through the second gate insulating layer and the inter-layer insulating layer.

2. The thin film transistor of claim 1, wherein the semiconductor layer pattern is a polycrystalline silicon layer pattern.

3. The thin film transistor of claim 1, wherein the semiconductor layer pattern of the first region is a channel region, a source region and a drain region, and the semiconductor layer pattern of the second region is a bottom electrode of a lower capacitor.

4. The thin film transistor of claim 1, wherein the first gate insulating layer pattern is formed of any one of a silicon oxide layer and a silicon nitride layer.

5. The thin film transistor of claim 4, wherein the first gate insulating layer pattern is about 400 Å

to about 1,000 Å

thick.

6. The thin film transistor of claim 1, wherein the second gate insulating layer is formed of any one of a silicon oxide layer and a silicon nitride layer.

7. The thin film transistor of claim 6, wherein the second gate insulating layer is about 200 Å

to about 800 Å

thick.

8. The thin film transistor of claim 1, wherein the first conductive layer pattern of the first region is a gate electrode, and the first conductive layer pattern of the second region is a top electrode of a lower capacitor and a bottom electrode of an upper capacitor.

9. The thin film transistor of claim 1, wherein the second conductive layer pattern of the first region is a source electrode and a drain electrode, and the second conductive layer pattern of the second region is a top electrode of an upper capacitor.

18. A flat panel display device comprising the thin film transistor of claim 1.

10. A method of fabricating a thin film transistor, comprising:

forming a polycrystalline silicon layer pattern in a first region and a second region of a substrate;

forming a first gate insulating layer on the substrate;

forming a photoresist layer pattern protecting a channel region of the polycrystalline silicon layer pattern of the first region;

doping the polycrystalline silicon layer pattern of the first region and the second region using the photoresist layer pattern as a mask to form a source region and a drain region in the first region and to form a first electrode in the second region;

etching the first gate insulating layer using the photoresist layer pattern as a mask to form a first gate insulating layer pattern and then removing the photoresist layer pattern;

forming a second gate insulating layer on the substrate;

forming a gate electrode in the first region of the substrate, and a second electrode in the second region of the substrate;

forming an inter-layer insulating layer on the substrate;

etching the inter-layer insulating layer and the second gate insulating layer to expose the source region and the drain region; and

forming a source electrode and a drain electrode coupled to the source region and the drain region, respectively, and forming a third electrode in the second region.

11. The method of claim 10, wherein the first electrode is a bottom electrode of a lower capacitor.

12. The method of claim 10, wherein the first gate insulating layer is formed of any one of a silicon oxide layer and a silicon nitride layer.

13. The method of claim 12, wherein the first gate insulating layer is about 400 Å

to about 1,000 Å

thick.

14. The method of claim 10, wherein the second gate insulating layer is formed of any one of a silicon oxide layer and a silicon nitride layer.

15. The method of claim 14, wherein the second gate insulating layer is about 200 Å

to about 800 Å

thick.

16. The method of claim 10, wherein the second electrode is a top electrode of a lower capacitor and a bottom electrode of an upper capacitor.

17. The method of claim 10, wherein the third electrode is a top electrode of an upper capacitor.

19. A thin film transistor, comprising:

a substrate having a first region and a second region;

a semiconductor layer pattern formed in the first region and the second region;

a first conductive layer pattern formed above a channel region of the semiconductor layer pattern of the first region and above the semiconductor layer pattern of the second region;

a second conductive layer pattern formed in the first region and above the first conductive layer pattern of the second region,

wherein a first gap between the first conductive layer pattern and the semiconductor layer pattern of the first region is greater than a second gap between the first conductive layer pattern and the semiconductor layer pattern of the second region.

20. The thin film transistor of claim 19, wherein the first gap is formed by a first gate insulating layer pattern formed on the channel region and a second gate insulating layer formed on the substrate, and the second gap is formed by the second gate insulating layer.