HIGH VOLTAGE DEVICE AND HIGH VOLTAGE DEVICE FOR ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT

• US 20050285198A1
• Filed: 09/30/2004
• Published: 12/29/2005
• Est. Priority Date: 06/25/2004
• Status: Active Grant

• Current Assignee: Novatek Microelectronics Corporation (Novatek Microelectronics Corp Limited)
• Original Assignee: Novatek Microelectronics Corporation (Novatek Microelectronics Corp Limited)
• Inventors: Chang, Chyh-Yih, Hsien, Li-Jen
• Granted Patent: US 7,067,887 B2
• Time in Patent Office: Days
• US Class Current: 257/360
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A high voltage device for an electrostatic discharge protection circuit is provided. A silicon layer is disposed in a substrate. A first type well and a second type well are disposed in the silicon layer. A lightly doped region of a second type well is located next to the first type well. A heavily doped region of the second type well is located underneath a portion of the first type well and the lightly doped region. A gate structure is disposed over a portion of the first type well and the lightly doped region. A second type first doped region and a second type second doped region are disposed in the lightly doped region and the first type well on each side of the gate structure. An isolation structure is disposed in the lightly doped region. A first type doped region is disposed in the first type well.

Claims

1. A high voltage device for an electrostatic discharge protection circuit, comprising:

a first type substrate;

a first type epitaxial silicon layer disposed in the first type substrate;

a first type well disposed in the first type epitaxial silicon layer;

a second type well disposed in the first type epitaxial silicon layer, wherein the second type well comprises a second type lightly doped region and a second type heavily doped region, the second type lightly doped region is located next to the first type well and the second heavily doped region is located underneath a portion of the first type well and the second type lightly doped region, wherein the first type well adjoins with the second heavily doped region;

a gate structure disposed on a portion of the first type well and the second typo lightly doped region;

a second type first doped region and a second type second doped region disposed in the second type lightly doped region and the first type well on each side of the gate structure respectively;

a first isolation structure disposed in the second type lightly doped region and between the gate structure and the second type first doped region; and

a first type doped region disposed in the first type well and adjacent to the second type second doped region.

2. The high voltage device of claim 1, wherein the second type lightly doped region, the first type well and the second type second doped region together constitute a parasitic bipolar transistor, and the second type heavily doped region, the first type well and the second type second doped region together constitute another parasitic bipolar transistor so that a pulse current entering from the second type first doped region is able to channel away through the second type second doped region after passing through the two parasitic bipolar transistors.

3. The high voltage device of claim 2, wherein the PN junction between the second type heavily doped region and the first type well has a smaller breakdown voltage than the PN junction between the second type lightly doped region and the first type well, and the breakdown voltage of the PN junction between the second type heavily doped region and the first type well is the breakdown voltage of the electrostatic discharge protection circuit.

4. The high voltage device of claim 1, further comprises a second isolation structure disposed in the first type well and between the first type doped region and the second type second doped region.

5. The high voltage device of claim 4, wherein the second isolation structure comprises a field oxide isolation structure or a shallow trench isolation (STI) structure.

6. The high voltage device of claim 1, wherein the first isolation structure comprises a field oxide isolation structure or a shallow trench (STI structure.

7. The high voltage device of claim 1, wherein the second type first doped region, the second type lightly doped region and the second type heavily doped region together serves as a drain and the second type second doped region serves as a source.

8. The high voltage device of claim 1, wherein the second type lightly doped region comprises a high voltage second type well.

9. The high voltage device of claim 1, wherein the second type heavily doped region comprises a second type buried layer.

10. The high voltage device of claim 1, wherein first type is a P-type and the second type is an N-type.

17. The high voltage device of claim 1 wherein the second type first doped region, the second type lightly doped region and the second type heavily doped region together serves as a drain and the second type second doped region serves as a source.

11. A high voltage device, comprising:

a first type substrate;

a first type epitaxial silicon layer disposed in the first type substrate;

a first type well disposed in the first type epitaxial silicon layer;

a second type well disposed in the first type epitaxial silicon layer, wherein the second type well comprises a second type lightly doped region and a second type heavily doped region, the second type lightly doped region is located next to the first type well and the second heavily doped region is located underneath a portion of the first type well and the second type lightly doped region, wherein the first type well adjoins with the second heavily doped region;

a gate structure disposed on a portion of the first type well and the second type lightly doped region;

a second type first doped region and a second type second doped region disposed in the second type lightly doped region and the first type well on each side of the gate structure respectively;

a first isolation structure disposed in the second type lightly doped region and between the gate structure and the second type first doped region; and

a first type doped region disposed in the first type well and adjacent to the second type second doped region.

12. The high voltage device of claim 11, further comprises a second isolation structure disposed in the first type well and between the first type doped region and the second type second doped region.

13. The high voltage device of claim 12, wherein the second isolation structure comprises a field oxide isolation structure or a shallow trench isolation (STD structure.

14. The high voltage device of claim 11, wherein the first isolation structure comprises a field oxide isolation structure or a shallow trench (STI) structure.

15. The high voltage device of claim 11, wherein the high voltage device has a variety of applications in the design of circuits.

16. The high voltage device of claim 15, wherein the high voltage device is used inside display driver ICs, power supplies, power administrators, telecommnunications, automobile electronics and industrial controls.

18. The high voltage device of claim 11, wherein the second type lightly doped region comprises a high voltage second type well.

19. The high voltage device of claim 11, wherein the second type heavily doped region comprises a second type buried layer.

20. The high voltage device of claim 11, wherein first type is a P-type and the second type is an N-type.