Integrated transistor module and method of fabricating same

• US 20050285238A1
• Filed: 06/24/2004
• Published: 12/29/2005
• Est. Priority Date: 06/24/2004
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Noquil, Jonathan A., Joshi, Rajeev D., Tangpuz, Consuelo N.
• Granted Patent: US 7,501,702 B2
• Time in Patent Office: Days
• US Class Current: 257/673
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/072 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1306 Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H02M 3/003 Constructional details, e.g. physical layout, assembly, wiring or busbar connections

Abstract

An integrated transistor module includes a lead frame that defines at least one low-side land and at least one high-side land. A stepped portion of the lead frame mechanically and electrically interconnects the low-side and high-side lands. A low-side transistor is mounted upon the low-side land with its drain electrically connected to the low-side land. A high-side transistor is mounted upon the high-side land with its source electrically connected to the high-side land.

Claims

1. An integrated transistor module, comprising:

a lead frame defining at least one low-side land and at least one high-side land, a stepped portion of said lead frame mechanically and electrically interconnecting said low-side and high-side lands;

a low-side transistor mounted upon said low-side land, a drain of said transistor being electrically connected to said low-side land; and

a high-side transistor mounted upon said high-side land, a source of said high-side transistor electrically connected to said high-side land.

2. The integrated transistor module of claim 1, wherein said lead frame comprises a conductive metal.

3. The integrated transistor module of claim 2, wherein said low-side and said high-side transistor comprise metal oxide semiconductor field effect transistors.

4. The integrated transistor module of claim 2, wherein said high-side transistor is flip-chip mounted to said high-side land.

5. The integrated transistor module of claim 2, wherein said low-side transistor is contained within a ball grid array package, said package being mounted to said low-side land.

6. The integrated transistor module of claim 2, further comprising a molded portion covering a side of said substrate opposite said high-side land, said molding having an upper surface that is substantially coplanar relative to a side of said substrate opposite said low-side land.

7. The integrated transistor module of claim 6, further comprising a heat sink thermally coupled to the side of said substrate opposite said high-side land and thereby to said low-side and said high-side transistors.

8. The integrated transistor of claim 7, wherein said heat sink extends over said molded portion.

9. A synchronous buck converter, comprising:

an integrated subassembly including a lead frame, at least one low-side transistor and at least one high-side transistor, said lead frame defining at least one low-side land and at least one high-side land, a stepped portion of said lead frame mechanically and electrically interconnecting said low-side and high-side lands, said low-side transistor mounted upon said low-side land, a drain of said transistor being electrically connected to said low-side land, said high-side transistor mounted upon said high-side land, a source of said high-side transistor electrically connected to said high-side land.

10. The synchronous buck converter of claim 9, wherein said lead frame comprises a conductive metal.

11. The synchronous buck converter of claim 10, wherein said low-side and said high-side transistor comprise metal oxide semiconductor field effect transistors.

12. The synchronous buck converter of claim 10, wherein said high-side transistor is flip-chip mounted to said high-side land.

13. The synchronous buck converter of claim 10, wherein said low-side transistor is contained within a ball grid array package, said package being mounted to said low-side land.

14. The synchronous buck converter of claim 10, further comprising a molded portion covering a side of said substrate opposite said high-side land, said molding having an upper surface that is substantially coplanar relative to a side of said substrate opposite said low-side land.

15. The synchronous buck converter of claim 14, further comprising a heat sink thermally coupled to the side of said substrate opposite said high-side land and thereby to said low-side and said high-side transistors.

16. The synchronous buck converter of claim 15, wherein said heat sink extends over said molded portion.

17. An integrated subassembly, comprising:

a lead frame defining at least one low-side land and at least one high-side land, a stepped portion of said lead frame mechanically and electrically interconnecting said low-side and high-side lands;

a high-side transistor mounted upon said high-side land, a source of said high-side transistor electrically connected to said high-side land; and

a molded portion covering a side of said substrate opposite said high-side land, said molding having an upper surface that is substantially coplanar relative to a side of said substrate opposite said low-side land.

18. The integrated transistor module of claim 17, wherein said lead frame comprises a conductive metal.

19. The integrated transistor module of claim 17, wherein said high-side transistor comprises a metal oxide semiconductor field effect transistor.

20. The integrated subassembly of claim 17, wherein said high-side transistor is flip-chip mounted to said high-side land.

21. A method of fabricating an integrated transistor module, comprising:

forming a leadframe that defines at least one low-side land and at least one high-side land vertically offset from said low-side land;

enclosing in an electrically insulating material a portion of said leadframe proximate said high-side land, an upper surface of said insulating material on a side of said leadframe that is opposite said high-side land being substantially coplanar relative to a side of said leadframe opposite said low-side land; and

mounting a high-side transistor upon said high-side land, a source of said high-side transistor being electrically connected to said high-side land.

22. The method of claim 21, comprising the further step of mounting a low-side transistor upon said low-side land, a drain of said low-side transistor electrically connected to said low-side land, said leadframe electrically interconnecting said source of said high-side transistor with said drain of said low-side transistor.

23. The method of claim 22, wherein said high-side transistor is flip-chip mounted upon said high-side land.

24. The method of claim 22, wherein said low-side transistor is contained within a ball grid array package.