DA converter circuit provided with DA converter of segment switched capacitor type

• US 20050285768A1
• Filed: 06/22/2005
• Published: 12/29/2005
• Est. Priority Date: 06/23/2004
• Status: Active Grant

• Current Assignee: Semiconductor Technology Academic Research Center
• Original Assignee: Semiconductor Technology Academic Research Center
• Inventors: Kobayashi, Haruo, Wada, Atsushi, Hagiwara, Hiroyuki, San, Hao
• Granted Patent: US 7,095,350 B2
• Time in Patent Office: Days
• US Class Current: 341/144
• CPC Class Codes: H03M 1/0665 using data dependent selection of the elements, e.g. data weighted averaging
• CPC Class Codes: H03M 1/806 with equally weighted capacitors which are switched by unary decoded digital signals
• CPC Class Codes: H03M 3/43 the quantiser being a single bit one
• CPC Class Codes: H03M 3/464 Details of the digital/analogue conversion in the feedback path

Abstract

A DA converter circuit is provided for use in a ΔΣ AD modulator. The DA converter circuit includes a DA converter of segment switched capacitor type. The DA converter includes an operational amplifier, capacitors as connected in parallel to each other to supply electric charges to the operational amplifier, an electrically charging switch for switching of electrically charging electric charges onto the respective capacitors or not, and an electrically discharging switch for switching or not electrically discharging electric charges from the respective capacitors or not. A switch device performs either one of the electrically charging, the electrically discharging, grounding, and polarity inversion onto the respective capacitors. A controller controls the electrically charging switch, the electrically discharging switch and the switch device to execute a process of second-order DWA algorithm for performing a second-order noise shaping of a non-linearity of the DA converter circuit.

Claims

1. A DA converter circuit including a DA converter of segment switched capacitor type, said DA converter comprising:

(a) an operational amplifier having a feedback capacity,

(b) a plurality of M=2^L capacitors which are connected in parallel to each other so as to supply electric charges to the operational amplifier;

(c) an electrically charging switch for switching over between performing and not performing of electrically charging electric charges onto the respective capacitors; and

(d) an electrically discharging switch for switching over between performing and not performing of electrically discharging electric charges from the respective capacitors, and

wherein the DA converter circuit further comprises;

a switch device for performing either one of the electrically charging, the electrically discharging, grounding, and polarity inversion onto the respective capacitors; and

a controller for controlling the electrically charging switch, the electrically discharging switch and the switch device so as to execute a process of second-order DWA algorithm for performing a second-order noise shaping of a non-linearity of the DA converter circuit for a low-pass Δ

Σ

AD modulator, using the following operations;

(A) a “

+2”

operation for performing the electrically charging and the electrically discharging twice onto the respective capacitors for a predetermined time interval to generate an output voltage which is a voltage of +2 times a predetermined reference output voltage;

(B) a “

+1”

operation for performing the electrically charging and the electrically discharging once onto the respective capacitors for the time interval to generate an output voltage which is a voltage of +1 times the reference output voltage;

(C) a “

0”

operation for not performing any electrically charging and electrically discharging onto the respective capacitors for the time interval to generate an output voltage which is a voltage of a grounding electric potential; and

(D) a “

−

1”

operation for performing the electrically charging once onto the respective capacitors and thereafter inverting polarities of the respective capacitors for the time interval to generate an output voltage which is a voltage of −

1 times the reference output voltage.

2. The DA converter circuit as claimed in claim 1,

wherein the plurality of M=2^L capacitors are equivalently constituted in a ring shape, and

wherein said controller controls said electrically charging switch, said electrically discharging switch and said switch device by executing the following steps of:

(a) based on input data D(n), calculating control parameters for controlling said switch device of the respective capacitors using the second-order DWA algorithm, said control parameters including;

(a1) a positive-side pointer indicated value P₀₊(n);

(a2) a positive-side signal starting position S₀₊(n);

(a3) a positive-side allocation number A₀₊(n);

(a4) a negative-side pointer indicated value P₀₋

(n);

(a5) a negative-side signal starting position S₀₋

(n); and

(a6) a negative-side allocation number A₀₋

(n),

(b) in respective capacity cells including said respective capacitors, and said switch device connected to said respective capacitors, allocating a “

positive digit”

to S₀₊(n)-th, mod_M(S₀₊(n)+1)-th, mod_M(S₀₊(n)+2)-th, . . . , and mod_M(S₀₊(n)+A₀₊(n)−

1)-th capacity cells, and allocating a “

negative digit”

to S₀₋

(n)-th, mod_M(S₀₋

(n)+1)-th, mod_M(S₀₋

(n)+2)-th, . . . , and mod_M(S₀₋

(n)+A₀₋

(n)−

1)-th capacity cells;

(c) setting a number of times of allocations of the positive digit to a m-th capacity cell to Nmp, and setting a number of times of allocations of the negative digit to the m-th capacity cell to Nmn; and

(d) (d1) setting the “

+2”

operation onto the m-th capacity cell when Nmp=Nmn+2;

(d2) setting the “

+1”

operation onto the m-th capacity cell when Nmp=Nmn+1, (d3) setting the “

0”

operation onto the m-th capacity cell when Nmp=Nmn, and (d4) setting the “

−

1”

operation onto the m-th capacity cell in any case other than the foregoing cases.

3. The DA converter circuit as claimed in claim 1,

wherein L=3,

wherein said DA converter comprises a number m=8 of capacitors, and

wherein said DA converter circuit is of eight bits.

4. The DA converter circuit as claimed in claim 2,

wherein L=3,

wherein said DA converter comprises a number m=8 of capacitors, and

wherein said DA converter circuit is of eight bits.

5. A Δ

Σ

AD modulator comprising;

a DA converter circuit;

a subtracter for subtracting a signal outputted from the DA converter circuit from an inputted analogue signal and outputting a signal having a subtraction result;

a low-pass filter for performing a predetermined low-pass filtering process onto the analogue signal outputted from the subtracter and outputting a filtered signal; and

an AD converter circuit for AD-converting the analogue signal outputted from the low-pass filter into a digital signal and outputting the AD-converted digital signal and further outputting the digital signal to the subtracter via the DA converter circuit,

wherein said DA converter circuit includes a DA converter of segment switched capacitor type,

wherein said DA converter comprising;

(a) an operational amplifier having a feedback capacity;

(b) a plurality of M=2^L capacitors which are connected in parallel to each other so as to supply electric charges to the operational amplifier;

(c) an electrically charging switch for switching over between performing and not performing of electrically charging electric charges onto the respective capacitors; and

(d) an electrically discharging switch for switching over between performing and not performing of electrically discharging electric charges from the respective capacitors, and

wherein the DA converter circuit further comprises;

a switch device for performing either one of the electrically charging, the electrically discharging operation, grounding, and polarity inversion onto the respective capacitors; and

a controller for controlling the electrically charging switch, the electrically discharging switch and the switch device so as to execute a process of second-order DWA algorithm for performing a second-order noise shaping of a non-linearity of the DA converter circuit for a low-pass Δ

Σ

AD modulator, using the following operations;

(A) a “

+2”

operation for performing the electrically charging and the electrically discharging twice onto the respective capacitors for a predetermined time interval to generate an output voltage which is a voltage of +2 times a predetermined reference output voltage;

(B) a “

+1”

operation for performing the electrically charging and the electrically discharging once onto the respective capacitors for the time interval to generate an output voltage which is a voltage of +1 times the reference output voltage;

(C) a “

0”

operation for not performing any electrically charging and electrically discharging onto the respective capacitors for the time interval to generate an output voltage which is a voltage of a grounding electric potential; and

(D) a “

−

1”

operation for performing the electrically charging once onto the respective capacitors and thereafter inverting polarities of the respective capacitors for the time interval to generate an output voltage which is a voltage of −

1 times the reference output voltage.

6. The Δ

Σ

AD modulator as claimed in claim 5,

wherein the plurality of M=2^L capacitors are equivalently constituted in a ring shape, and

wherein said controller controls said electrically charging switch, said electrically discharging switch and said switch device by executing the following steps of;

(a) based on input data D(n), calculating control parameters for controlling said switch device of the respective capacitors using the second-order DWA algorithm, said control parameters including;

(a1) a positive-side pointer indicated value P₀₊(n);

(a2) a positive-side signal starting position S₀₊(n);

(a3) a positive-side allocation number A₀₊(n);

(a4) a negative-side pointer indicated value P₀₋

(n);

(a5) a negative-side signal starting position S₀₋

(n); and

(a6) a negative-side allocation number A₀₋

(n),

(b) in respective capacity cells including said respective capacitors, and said switch device connected to said respective capacitors, allocating a “

positive digit”

to S₀₊(n)-th, mod_M(S₀₊(n)+1)-th, mod_M(S₀₊(n)+2)-th, . . . , and mod_M(S₀₊(n)+A₀₊(n)−

1)-th capacity cells, and allocating a “

negative digit”

to S₀₋

(n)-th, mod_M(S₀₋

(n)+1)-th, mod_M(S₀₋

(n)+2)-th, . . . , and mod_M(S₀₋

(n)+A₀₋

(n)−

1)-th capacity cells;

(c) setting a number of times of allocations of the positive digit to a m-th capacity cell to Nmp, and setting a number of times of allocations of the negative digit to the m-th capacity cell to Nmn; and

(d) (d1) setting the “

+2”

operation onto the m-th capacity cell when Nmp=Nmn+2;

(d2) setting the “

+1”

operation onto the m-th capacity cell when Nmp=Nmn+1, (d3) setting the “

0”

operation onto the m-th capacity cell when Nmp=Nmn, and (d4) setting the “

−

1”

operation onto the m-th capacity cell in any case other than the foregoing cases.

7. The Δ

Σ

AD modulator as claimed in claim 5,

wherein L=3,

wherein said DA converter comprises a number m=8 of capacitors, and

wherein said DA converter circuit is of eight bits.

8. The Δ

Σ

AD modulator as claimed in claim 6,

wherein L=3,

wherein said DA converter comprises a number m=8 of capacitors, and

wherein said DA converter circuit is of eight bits.