Liquid crystal display device and method of fabricating the same

• US 20050286003A1
• Filed: 06/28/2005
• Published: 12/29/2005
• Est. Priority Date: 06/29/2004
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Choi, Seung Chan, Lee, Hyun Kyu
• Granted Patent: US 7,557,886 B2
• Time in Patent Office: Days
• US Class Current: 349/141
• CPC Class Codes: G02F 1/134345 Subdivided pixels, e.g. for grey scale or redundancy
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 2201/121 common or background

Abstract

A liquid crystal display device includes first and second substrates; a gate line and a data line on the first substrate to define a unit pixel having first and second sub-pixel regions; first and second switching devices in the first and second sub-pixel regions; a plurality of first and second common electrodes in the first and second sub-pixel regions; a plurality of first and second pixel electrodes in the first and second sub-pixel regions; a common line shared by the unit pixel and an adjacent unit pixel; and a liquid crystal layer between the first and second substrates.

Claims

1. A liquid crystal display (LCD) device comprising:

first and second substrates;

a gate line and a data line on the first substrate to define a unit pixel having first and second sub-pixel regions;

first and second switching devices in the first and second sub-pixel regions;

a plurality of first and second common electrodes in the first and second sub-pixel regions;

a plurality of first and second pixel electrodes in the first and second sub-pixel regions;

a common line shared by the unit pixel and an adjacent unit pixel; and

a liquid crystal layer between the first and second substrates.

2. The device of claim 1, wherein the first and second switching devices share a gate electrode, a source electrode and a semiconductor layer.

3. The device of claim 2, wherein the gate electrode is formed as a part of one gate line.

4. The device of claim 2, wherein the source electrode extends from one data line.

5. The device of claim 2, wherein the first switching device further comprises a first drain electrode, and the second switching device further comprises a second drain electrode.

6. The device of claim 1, wherein the first and second sub-pixel regions are symmetrical with respect to the gate line.

7. The device of claim 1, wherein the first common electrode and the first pixel electrode form an in-plane electric field in the first sub-pixel region, and the second common electrode and the second pixel electrode form an in-plane electric field in the second sub-pixel region.

8. The device of claim 7, wherein the in-plane electric field forms an inclination angle of about 0 to about 45°

with respect to the data line.

9. The device of claim 8, further comprising alignment layers on the first and second substrates.

10. The device of claim 9, wherein a rubbing direction of the alignment layer is perpendicular to the data line.

11. The device of claim 1, wherein the first and second pixel electrodes partially overlap upper and lower edges of the gate line.

12. The device of claim 1, wherein the first and second pixel electrodes overlap edges of adjacent common lines.

13. The device of claim 1, wherein the common line is formed near an interface between adjacent unit pixels.

14. The device of claim 13, wherein a common signal substantially simultaneously applies to a second common electrode of a unit pixel defined by the n^th gate line and a first common electrode of a unit pixel defined by the n+1^th gate line.

15. The device of claim 13, wherein the common line is formed of a metal layer.

16. The device of claim 1, further comprising a black matrix on at least one of the first and second substrates corresponding to the first and second switching devices.

17. The device of claim 16, wherein the black matrix includes a column spacer.

18. The device of claim 17, wherein the black matrix forms on at least one of the first and second substrates except at least one of the first and second substrates corresponding to the gate line and the data line.

19. The device of claim 1, further comprising:

a first common electrode connection line electrically connecting the plurality of first common electrodes; and

a second common electrode connection line electrically connecting the plurality of second common electrodes.

20. The device of claim 19, further comprising:

a first pixel electrode connection line electrically connecting the plurality of first pixel electrodes; and

a second pixel electrode connection line electrically connecting the plurality of second pixel electrodes.

21. The device of claim 20, wherein the first common electrode connection line and the first pixel electrode connection line overlap to form a first storage capacitor, and the second common electrode connection line and the second pixel electrode connection line overlap to form a second storage capacitor.

22. The device of claim 1, wherein the first and second pixel electrodes are connected to each other at an upper portion of the gate line.

23. The device of claim 1, wherein the first and second common electrodes are formed as a plate shape on the first substrate and the first and second pixel electrodes have a plurality of slits.

24. The device of claim 23, wherein intervals between the slits of the first and second pixel electrodes are narrow so as to generate a fringe electric field.

25. The device of claim 24, wherein a distance between the first common electrode and the first pixel electrode and a distance between the second common electrode and the second pixel electrode are smaller than a distance between the first substrate and the second substrate.

26. The device of claim 25, wherein the first common electrode and the first pixel electrode, and the second common electrode and the second pixel electrode form an in-plane electric field, the electric field being formed substantially at an inclination angle of 0 to 45°

with respect to the data line.

27. The device of claim 26, further comprising alignment layers on the first and second substrates.

28. The device of claim 27, wherein a rubbing direction of one of the alignment layers is perpendicular to the data line.

29. The device of claim 25, wherein the first pixel electrode and the second pixel electrode are connected to each other at an upper portion of the gate line.

30. The device of claim 23, wherein the first and second common electrodes and the first and second pixel electrodes are formed of a transparent conductive material.

31. The device of claim 30, wherein the common line is formed at an interface between adjacent unit pixels.

32. The device of claim 31, wherein a second common electrode of a unit pixel defined by the n^th gate line and a first common electrode of a unit pixel defined by the n+1^th gate line are formed of a transparent conductive material and formed at the same time with the common line.

33. The device of claim 1, wherein the second substrate further comprises a color filter.

34. A method for fabricating a liquid crystal display (LCD) device comprising:

preparing a first substrate and a second substrate;

forming a first metal material on the first substrate;

patterning the first metal material using a first mask to form a gate line, a gate electrode, a common electrode and a common line;

forming a gate insulation film, an amorphous silicon layer and a n+ amorphous silicon layer on the first substrate;

patterning the amorphous silicon layer and the n+ amorphous silicon layer using a second mask to form a semiconductor layer and an ohmic contact layer;

forming a second metal material on the first substrate;

patterning the second metal material using a third mask to form a data line, a source electrode and first and second drain electrodes;

forming a passivation film on the first substrate;

patterning the passivation film using a fourth mask to form a contact hole;

forming a transparent conductive material on the passivation film; and

patterning the transparent conductive material using a fifth mask to form a pixel electrode.

35. The method of claim 34, further comprising:

forming an organic film on the pixel electrode; and

patterning the organic film using a sixth mask to form a spacer.

36. The method of claim 34, further comprising forming a liquid crystal layer between the first and second substrates.

37. A method for fabricating a liquid crystal display device comprising:

preparing a first substrate and a second substrate;

forming a first metal material on the first substrate;

patterning the first metal material using a first mask to form a gate line, a gate electrode and a common line;

forming a transparent conductive material on the first substrate;

patterning the transparent conductive material using a second mask to form a common electrode;

forming a gate insulation film, an amorphous silicon layer and a n+ amorphous silicon layer on the first substrate;

patterning the amorphous silicon layer and the n+ amorphous silicon layer using a third mask to form a semiconductor layer and an ohmic contact layer;

forming a second metal material on the first substrate;

patterning the second metal material using a fourth mask to form a data line, a source electrode and first and second drain electrodes;

forming a passivation film on the first substrate;

patterning the passivation film using a fifth mask to form a contact hole;

forming a transparent conductive material on the passivation film; and

patterning the transparent conductive material using a sixth mask to form a pixel electrode.

38. The method of claim 37, further comprising:

forming an organic film on the pixel electrode; and

patterning the organic film using a sixth mask to form a spacer.

39. The method of claim 37, further comprising forming a liquid crystal layer between the first and second substrates.

40. A method for fabricating a liquid crystal display device comprising:

preparing a first substrate and a second substrate;

forming a first metal material on the first substrate;

patterning the first metal material using a first mask to form a gate line and a gate electrode;

forming a transparent conductive material on the first substrate;

patterning the transparent conductive material using a second mask to form a common line and a common electrode;

forming a gate insulation film, an amorphous silicon layer and a n+ amorphous silicon layer on the first substrate;

patterning the amorphous silicon layer and the n+ amorphous silicon layer using a third mask to form a semiconductor layer and an ohmic contact layer;

forming a second metal material on the first substrate;

patterning the second metal material using a fourth mask to form a data line, a source electrode and first and second drain electrodes;

forming a passivation film on the first substrate;

patterning the passivation film using a fifth mask to form a contact hole;

forming a transparent conductive material on the passivation film; and

patterning the transparent conductive material using a sixth mask to form a pixel electrode.

41. The method of claim 40, further comprising:

forming an organic film on the pixel electrode; and

patterning the organic film using a sixth mask to form a spacer.

42. The method of claim 40, further comprising forming a liquid crystal layer between the first and second substrates.

43. The method of claim 40, wherein the transparent conductive material includes at least one of ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin Zinc Oxide) and TO (Tin Oxide).