Elongated features for improved alignment process integration

• US 20050286052A1
• Filed: 06/23/2004
• Published: 12/29/2005
• Est. Priority Date: 06/23/2004
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kay, Alex W., Huggins, Kevin, Weiss, Martin N., Irby, John H. IV
• Application Number:
  US10/875,081
• Publication Number:
  US 20050286052A1
• Time in Patent Office: Days
• US Class Current: 356/401
• CPC Class Codes: G03F 9/7076 Mark details, e.g. phase grating mark, temporary mark
• CPC Class Codes: H01L 21/76819 Smoothing of the dielectric planarisation of insulating materials per se H01L21/31051
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Improved integration of alignment or overlay and other processes. A substrate may have one or more alignment features, which may be included in alignment marks or overlay features. Elongated features such as dummification features may be used near the alignment features. For example, line-shaped dummification features may be used in an alignment region, where light from an alignment process may interact with both the alignment features and the elongated features. The elongated features may be in the same layer or a different layer than the alignment features.

Claims

1. A method, comprising:

forming a plurality of elongated features on one or more semiconductor parts, the elongated features each having an associated long dimension and an associated short dimension, the associated long dimension greater than the associated short dimension; and

forming a plurality of alignment features on at least one of the one or more semiconductor parts, the plurality of alignment features to define an alignment region, the alignment region bordered in a plane by a first outer alignment feature and a second outer alignment feature and extending downward, wherein a portion of at least one of the plurality of elongated features is included in the alignment region.

2. The method of claim 1, wherein the elongated features include dummification features formed on a substrate.

3. The method of claim 1, wherein one or more of the plurality of elongated features is at least partially positioned between a first alignment feature and a second alignment feature.

4. The method of claim 1, wherein the plurality of alignment features are formed in a current layer, and wherein the one or more of the plurality of elongated features are formed in a previous layer.

5. The method of claim 1, wherein the elongated features are line-shaped.

6. The method of claim 5, wherein each of the elongated features has a corresponding line width, and wherein at least one of the elongated features has a corresponding line width different than a different one of the elongated features.

7. The method of claim 5, wherein adjacent elongated features are separated by a space having a corresponding space width.

8. The method of claim 7, wherein a first corresponding space width for a first pair of adjacent elongated features is different than a second corresponding space width for a second pair of adjacent elongated features.

9. The method of claim 1, wherein the alignment features are configured to determine an alignment parameter of a lithography system.

10. The method of claim 1, wherein the alignment features are configured to determine an overlay parameter.

11. The method of claim 1, wherein the one or more semiconductor parts include at least one of a mask, a reticle, and the substrate.

12. A method, comprising:

transmitting light to a plurality of elongated alignment features having a long dimension along a first axis and a short dimension, wherein the transmitted light interacts with the plurality of alignment features during an alignment process;

transmitting the light to a plurality of elongated features each having an associated long dimension along a long axis and an associated short dimension, wherein the light interacts with at least one of the plurality of elongated features during the alignment process;

receiving light that has interacted with the plurality of alignment features and light that has interacted with the plurality of elongated features as received light; and

determining an alignment parameter based on the received light.

13. The method of claim 12, wherein the received light has been reflected from at least one of the plurality of alignment features.

14. The method of claim 12, wherein the received light comprises diffracted light that has been scattered by at least one of the plurality of alignment features.

15. The method of claim 14, wherein the diffracted light comprises at least one non-zeroth order diffracted light.

16. The method of claim 12, wherein the long axis of the plurality of alignment features and the long axis of the plurality of elongated features are substantially parallel.

17. The method of claim 16, wherein the plurality of elongated features are formed in a lower layer of an integrated circuit than the plurality of alignment features.

18. The method of claim 12, wherein the long axis of the plurality of alignment features and the long axis of the plurality of elongated features are substantially perpendicular.

19. The method of claim 12, wherein the alignment parameter is indicative of an alignment of a lithography system.

20. The method of claim 12, wherein the alignment parameter is indicative of an overlay between a first layer and a second layer of a circuit structure.

21. The method of claim 12, wherein the elongated features include dummification features.

22. An apparatus, comprising:

one or more semiconductor parts having a plurality of alignment features, the plurality of alignment features defining an alignment region, the alignment region extending from an outer edge of a first outer alignment feature to an outer edge of a second outer alignment feature on a current layer, the alignment region extending downward to one or more previous layers;

one or more elongated features positioned on one of the one or more semiconductor parts, the one or more elongated features at least partially within the alignment region.

23. The apparatus of claim 22, wherein the one or more elongated features are at least partially included in the alignment region on the current layer.

24. The apparatus of claim 22, wherein the one or more elongated features are at least partially included in the alignment region on a previous layer.

25. The apparatus of claim 22, wherein the one or more elongated features have a length and a width, the length at least three times the width.

26. The apparatus of claim 22, wherein the one or more elongated features are line-shaped.

27. The apparatus of claim 26, wherein the plurality of alignment features are line-shaped.

28. The apparatus of claim 22, wherein the one or more elongated features are substantially parallel to the plurality of alignment features.

29. The apparatus of claim 27, wherein the one or more elongated features are substantially perpendicular to the plurality of alignment features.

30. The apparatus of claim 22, wherein the plurality of alignment features are included in an alignment mark.

31. The apparatus of claim 22, wherein the plurality of alignment features are included in an overlay structure.

32. The apparatus of claim 22, wherein the one or more semiconductor parts include at least one of a mask, a reticle, and a semiconductor substrate.

33. The apparatus of claim 22, further including a lithography system, and wherein the one or more semiconductor parts are included in a lithography system.