Memory device with a data hold latch

• US 20050286327A1
• Filed: 06/10/2004
• Published: 12/29/2005
• Est. Priority Date: 06/10/2004
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Kenkare, Prashant U., Ramaraju, Ravindraraj, Hoekstra, George P.
• Granted Patent: US 7,349,266 B2
• Time in Patent Office: Days
• US Class Current: 365/202
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

A memory device includes a plurality of pairs of complimentary bit lines and a plurality of latch circuits. Each pair of the plurality of pairs of complimentary bit lines is coupled to a column of memory cells. Each latch circuit has an input coupled to a data line and a first output and a second output to provide complementary latched values dependent upon a value of the data line. For each latch of the plurality of latches, the first output is coupled to a first bit line of a pair of the plurality such that a value of the first bit line is continuously determined by the first output during memory device operation and the second output is coupled to a second bit line of the pair such that a value of the second bit line is continuously determined by the second output during memory device operation.

Claims

1. A memory device comprising:

a bit line;

a column of memory cells coupled to the bit line; and

a latch circuit having an input coupled to a data line and an output to provide a latched value dependent upon a value of the data line, the output is coupled to the bit line such that a value of the bit line is continuously determined by the output during memory device operation.

2. The memory device of claim 1 wherein the bit line is a write bit line.

3. The memory device of claim 2 further comprising:

a read bit line, the column of memory cells coupled to the read bit line.

4. The memory device of claim 1 further comprising:

a second bit line, the second bit line being a complementary bit line to the bit line, the column of memory cells coupled to the second bit line.

5. The memory device of claim 4 wherein:

the latch circuit includes a second output, the second output is coupled to the second bit line such that a value of the second bit line is continuously determined by the second output during memory device operation.

6. The memory device of claim 1 wherein:

the latch circuit includes a pair of cross coupled inverters;

the output of the latch circuit is coupled to an input of a first inverter of the pair and an output of the second inverter of the pair.

7. The memory device of claim 6 wherein the latch circuit includes a third inverter having an output connected to the output of the latch circuit and an input connected to the input of the first inverter of the pair and the output of the second inverter of the pair.

8. The memory device of claim 1 wherein the latch circuit includes a second input to receive a clock signal, wherein the latched value at the output of the latch circuit changes value dependent upon a value of the data line at a time determined by a change of state of the clock signal.

9. The memory device of claim 8 wherein a value of the bit line is changed only in response to a value on the data line at a time determined by the change in state of the clock signal.

10. The memory device of claim 8 further comprising:

a word line coupled to a memory cell of the column of memory cells to carry a write signal to the memory cell,

word line generation circuitry having an output coupled to the word line to provide the write signal, the word line generation circuitry including an input to receive a clock signal, wherein the write signal changes state at a time determined by a change of state of the clock signal received at the input of the word line generation circuitry;

wherein the clock signal received by the word line generation circuitry and the clock signal received at the second input of the latch are generated from a common clock signal.

11. The memory device of claim 10 wherein:

the value at the output of the latch circuit changes value dependent upon a value of the data line at a time determined by a change in the state of the common clock signal from a first state to a second state;

the write signal changes from a non write state to a write state at a time determined by a change of state of the common clock signal from the first state to the second state.

12. The memory device of claim 11 wherein:

the write signal changes from a write state to a non write state at a time determined by a change of state of the common clock signal from the second state to the first state.

13. The memory device of claim 1 further comprising:

a second bit line;

a second column of memory cells coupled to the second bit line;

a second latch circuit having an second input coupled to a second data line and a second output to provide a latched value dependent upon a value of the second data line, the second output of the second latch circuit is coupled to the second bit line such that a value of the second bit line is continuously determined by the second output during memory device operation.

14. The memory device of claim 13 wherein the column of memory cells includes a memory cell located in a same row as a memory cell of the second column of memory cells.

15. The memory device of claim 1 wherein the value of the bit line is changed only in response to a value of the data line.

16. The memory device of claim 1 wherein the memory device is characterized as a multi-port register file.

17. The memory device of claim 1 wherein the output is coupled to the bit line such that a value of the bit line is continuously determined by the output during memory device operation including all memory reads to a memory cell of the column.

18. An integrated circuit including a memory device of claim 1 wherein the integrated circuit further includes a processor core.

19. The memory device of claim 1 wherein reads and writes to memory cells of the column of memory cells are performed during memory device operation.

20. A method of operating a memory device comprising:

operating a memory device including performing a plurality of reads and a plurality of writes to memory cells of a column of memory cells;

continuously controlling a value of a bit line coupled to the column of memory cells using a latch output during the operating.

21. The method of claim 20 further comprising:

changing a value of the latch output in response to a value of a latch input at a time determined by a change in state of a clock signal from a first state to a second state.

22. The method of claim 20 further comprising:

writing a value to a memory cell of the column of memory cells, wherein the writing includes changing a state of the bit line.

23. The method of claim 22 wherein:

the writing includes changing the state of a write line coupled to the memory cell from a non write state to a write state.

24. The method of claim 23 wherein:

the changing the state of the bit line includes changing the state at a time determined by a change in state of a clock signal from a first state to a second state;

the changing the state of the write line further includes changing the state at a time determined by a change in state of the clock signal from the first state to the second state.

25. The method of claim 24 wherein the writing further includes changing the state of the write line to the non write state from the write state at a time determined by a change in state of the clock signal from the second state to the first state.

26. The method of claim 22 wherein the writing further includes changing the state of the write line to the non write state from the write state at a time determined by the change in state of the clock signal from the first state to the second state.

27. The method of claim 22 wherein the writing includes changing the state of the bit line from a first state to a second state, wherein the method further comprises:

writing another value to a memory cell of the column of memory cells after the writing, wherein the writing another value includes changing the state of the bit line, wherein no other writing to a memory cell of the column is performed in between the changing the state of the writing and the writing another value;

wherein the bit line remains at the second state from a time of the changing the state of the writing to the changing the state of the writing another value.

28. The method of claim 27 further comprising:

reading a value of a memory cell of the column after the writing and prior to the writing another value, wherein the bit line remains at the second state regardless of the value of the memory cell being read.

29. The method of claim 20 further comprising:

continuously controlling a value of a second bit line coupled to the column of memory cells with the latch output during the operating, the second bit line is a complementary bit line to the bit line.

30. The method of claim 20 wherein the operating the memory device further includes performing a plurality of reads and a plurality of writes to memory cells of a second column of memory cells, the method further comprises:

continuously controlling a value of a second bit line coupled to a second column of memory cells with a second latch output during the operating.

31. A memory device comprising:

a bit line;

a column of memory cells coupled to the bit line; and

a latch circuit having an input coupled to a data line and an output to provide a latched value dependent upon a value of the data line, the output is connected to the bit line.

32. The memory device of claim 31 further comprising:

a second bit line;

a second column of memory cells coupled to the second bit line;

a second latch circuit having a second input coupled to a second data line and a second output to provide a latched value dependent upon a value of the second data line, the second output is connected to the second bit line.

33. A memory device comprising:

a plurality of pairs of complimentary bit lines, wherein each pair of the plurality is coupled to a column of memory cells;

a plurality of latch circuits, each latch circuit having an input coupled to a data line and a first output and a second output to provide complementary latched values dependent upon a value of the data line;

wherein for each latch of the plurality, the first output is coupled to a first bit line of a pair of the plurality such that a value of the first bit line is continuously determined by the first output during memory device operation and the second output is coupled to a second bit line of the pair such that a value of the second bit line is continuously determined by the second output during memory device operation.

34. A memory device comprising:

a bit line;

a column of memory cells coupled to the bit line; and

a latch circuit having an input coupled to a data line and an output to provide a latched value dependent upon a value of the data line, the output is coupled to the bit line such that the value of the bit line changes if and only if a value at the output changes during memory device operation.