System and method for an asynchronous data buffer having buffer write and read pointers
First Claim
1. A read data synchronizing circuit for coupling read data from a memory device operating according to a memory device clock signal to a memory controller operating according to a core clock signal, the read data synchronizing circuit comprising:
- a data buffer coupled to the memory device and having a plurality of data locations at which read data are respectively stored;
a multiplexer coupled to the data buffer to selectively couple read data stored at respective data locations of the data buffer to an output terminal in accordance with a selection signal;
a write pointer circuit coupled to the memory device and the data buffer and adapted to generate a write pointer signal to sequentially select one of the plurality of data locations of the data buffer for storing read data received from the memory device responsive to a strobe signal provided by the memory device;
a read pointer circuit coupled to the multiplexer and adapted to generate responsive to the core clock signal a read pointer signal provided to the multiplexer to sequentially select one of the plurality of data locations of the buffer from which the read data stored therein is coupled to the output terminal of the multiplexer; and
a write-read pointer compare circuit coupled to the write and read pointer circuits to compare the write and read pointer signals and adapted to generate a write-read pointer offset signal indicative of the comparison.
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Accused Products
Abstract
A system and method for facilitating the adjustment of timing parameters between a memory controller operating in a first clock domain and a memory device operating in a second clock domain. A write pointer and a read pointer are monitored to provide a write-read pointer offset representing the timing between when read data is made available by the memory device and when the read data is retrieved by the memory controller. Based on the write-read pointer offset, adjustment to different timing parameters can be made.
147 Citations
62 Claims
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1. A read data synchronizing circuit for coupling read data from a memory device operating according to a memory device clock signal to a memory controller operating according to a core clock signal, the read data synchronizing circuit comprising:
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a data buffer coupled to the memory device and having a plurality of data locations at which read data are respectively stored;
a multiplexer coupled to the data buffer to selectively couple read data stored at respective data locations of the data buffer to an output terminal in accordance with a selection signal;
a write pointer circuit coupled to the memory device and the data buffer and adapted to generate a write pointer signal to sequentially select one of the plurality of data locations of the data buffer for storing read data received from the memory device responsive to a strobe signal provided by the memory device;
a read pointer circuit coupled to the multiplexer and adapted to generate responsive to the core clock signal a read pointer signal provided to the multiplexer to sequentially select one of the plurality of data locations of the buffer from which the read data stored therein is coupled to the output terminal of the multiplexer; and
a write-read pointer compare circuit coupled to the write and read pointer circuits to compare the write and read pointer signals and adapted to generate a write-read pointer offset signal indicative of the comparison. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A data synchronizing circuit for coupling data between a memory controller clocked in accordance with a core clock signal and a memory device clocked in accordance with a memory device clock signal, the data synchronizing circuit comprising:
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a data buffer having a plurality of memory locations at which to store data and a selection signal node, the data buffer coupled to the memory device to store read data at a respective one of the plurality of data locations selected in accordance with a selection signal;
a write pointer circuit coupled to the memory device to receive a data strobe signal and further coupled to the selection signal node of the data buffer to provide a selection signal to sequentially select a data location to which read data from the memory device is written in response to the data strobe signal;
a multiplexer having a plurality of input terminals coupled to a respective one of the plurality of data locations of the data buffer and further having an output terminal to which the input terminals are selectively coupled to couple read data from the data buffer to the output terminal according to a multiplexer selection signal applied to a multiplexer selection node;
a read pointer circuit having a clock node to which the core clock signal is applied and further having an output node coupled to the multiplexer selection node to provide the multiplexer selection signal to sequentially select the input terminals for coupling to the output terminal of the multiplexer responsive to the core clock signal; and
a pointer comparison circuit coupled to the write and read pointer circuits to compare to which one of the data locations read data received from the memory device are currently stored and from which one of the data locations read data are currently coupled to the output terminal of the multiplexer and generate a write-read pointer offset signal indicative of the comparison. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A memory hub, comprising:
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a link interface receiving memory requests for access to memory locations in at least one memory device;
a memory device interface adapted to couple memory requests to memory devices for access to at least one of the memory devices and to receive read data responsive to at least some of the memory requests;
a memory controller coupled to the link interface and the memory device interface, the memory controller adapted to couple memory requests to the memory device interface responsive to memory requests received from the link interface responsive to a core clock signal, the memory controller further adapted to adjust the timing at which read memory requests are coupled to the memory device interface responsive to a write-read pointer offset signal; and
a read data synchronizing circuit coupled to the memory device interface, the read synchronization module, and the memory controller, the read data synchronizing circuit coupling read data from the memory devices operating according to a memory device clock signal to the memory controller, the read data synchronizing circuit comprising;
a data buffer coupled to the memory device and having a plurality of data locations at which read data are respectively stored;
a multiplexer coupled to the data buffer to selectively couple read data stored at respective data locations of the data buffer to an output terminal in accordance with a selection signal;
a write pointer circuit coupled to the memory device and the data buffer and adapted to generate a write pointer signal to sequentially select one of the plurality of data locations of the data buffer for storing read data received from the memory device responsive to a strobe signal provided by the memory device;
a read pointer circuit coupled to the multiplexer and adapted to generate responsive to the core clock signal a read pointer signal provided to the multiplexer to sequentially select one of the plurality of data locations of the buffer from which the read data stored therein is coupled to the output terminal of the multiplexer; and
a write-read pointer compare circuit coupled to the write and read pointer circuits to compare the write and read pointer signals and adapted to generate and provide the write-read pointer offset signal indicative of the comparison to the memory controller. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23)
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24. A memory hub, comprising:
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a link interface receiving memory requests for access to memory locations in at least one memory device;
a memory device interface adapted to couple memory requests to memory devices for access to at least one of the memory devices and to receive read data responsive to at least some of the memory requests;
a memory controller coupled to the link interface and the memory device interface, the memory controller adapted to couple memory requests to the memory device interface responsive to memory requests received from the link interface responsive to a core clock signal, the memory controller further adapted to adjust the timing at which read memory requests are coupled to the memory device interface responsive to a write-read pointer offset signal; and
a read data synchronizing circuit coupled to the memory device interface, the read synchronization module, and the memory controller, the read data synchronizing circuit coupling read data from the memory devices operating according to a memory device clock signal to the memory controller, the read data synchronizing circuit comprising;
a data buffer having a plurality of memory locations at which to store data and a selection signal node, the data buffer coupled to the memory device to store read data at a respective one of the plurality of data locations selected in accordance with a selection signal;
a write pointer circuit coupled to the memory device to receive a data strobe signal and further coupled to the selection signal node of the data buffer to provide a selection signal to sequentially select a data location to which read data from the memory device is written in response to the data strobe signal;
a multiplexer having a plurality of input terminals coupled to a respective one of the plurality of data locations of the data buffer and further having an output terminal to which the input terminals are selectively coupled to couple read data from the data buffer to the output terminal according to a multiplexer selection signal applied to a multiplexer selection node;
a read pointer circuit having a clock node to which the core clock signal is applied and further having an output node coupled to the multiplexer selection node to provide the multiplexer selection signal to sequentially select the input terminals for coupling to the output terminal of the multiplexer responsive to the core clock signal; and
a pointer comparison circuit coupled to the write and read pointer circuits to compare to which one of the data locations read data received from the memory device are currently stored and from which one of the data locations read data are currently coupled to the output terminal of the multiplexer and generate a write-read pointer offset signal indicative of the comparison. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32)
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33. A memory module, comprising:
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a plurality of memory devices;
a memory bus coupled to the plurality of memory devices; and
a memory hub coupled to the plurality of memory devices through the memory bus, the memory hub, comprising;
a link interface receiving memory requests for access to memory locations in at least one memory device;
a memory device interface adapted to couple memory requests to memory devices for access to at least one of the memory devices and to receive read data responsive to at least some of the memory requests;
a memory controller coupled to the link interface and the memory device interface, the memory controller adapted to couple memory requests to the memory device interface responsive to memory requests received from the link interface responsive to a core clock signal, the memory controller further adapted to adjust the timing at which read memory requests are coupled to the memory device interface responsive to a write-read pointer offset signal; and
a read data synchronizing circuit coupled to the memory device interface, the read synchronization module, and the memory controller, the read data synchronizing circuit coupling read data from the memory devices operating according to a memory device clock signal to the memory controller, the read data synchronizing circuit comprising;
a data buffer coupled to the memory device and having a plurality of data locations at which read data are respectively stored;
a multiplexer coupled to the data buffer to selectively couple read data stored at respective data locations of the data buffer to an output terminal in accordance with a selection signal;
a write pointer circuit coupled to the memory device and the data buffer and adapted to generate a write pointer signal to sequentially select one of the plurality of data locations of the data buffer for storing read data received from the memory device responsive to a strobe signal provided by the memory device;
a read pointer circuit coupled to the multiplexer and adapted to generate responsive to the core clock signal a read pointer signal provided to the multiplexer to sequentially select one of the plurality of data locations of the buffer from which the read data stored therein is coupled to the output terminal of the multiplexer; and
a write-read pointer compare circuit coupled to the write and read pointer circuits to compare the write and read pointer signals and adapted to generate and provide the write-read pointer offset signal indicative of the comparison to the memory controller. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40, 41)
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42. A processor-based system, comprising:
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a processor having a processor bus;
a system controller coupled to the processor bus, the system controller having a peripheral device port, the system controller further comprising a controller coupled to a system memory port;
at least one input device coupled to the peripheral device port of the system controller;
at least one output device coupled to the peripheral device port of the system controller;
at least one data storage device coupled to the peripheral device port of the system controller;
a memory bus coupled to the system controller for transmitting memory requests and responses thereon; and
a plurality of memory modules coupled to the memory bus, each of the modules having;
a plurality of memory devices; and
a memory hub coupled to the memory devices through a memory device bus to access the memory devices, the memory hub comprising;
a link interface receiving memory requests for access to memory locations in at least one memory device;
a memory device interface adapted to couple memory requests to memory devices for access to at least one of the memory devices and to receive read data responsive to at least some of the memory requests;
a memory controller coupled to the link interface and the memory device interface, the memory controller adapted to couple memory requests to the memory device interface responsive to memory requests received from the link interface responsive to a core clock signal, the memory controller further adapted to adjust the timing at which read memory requests are coupled to the memory device interface responsive to a write-read pointer offset signal; and
a read data synchronizing circuit coupled to the memory device interface, the read synchronization module, and the memory controller, the read data synchronizing circuit coupling read data from the memory devices operating according to a memory device clock signal to the memory controller, the read data synchronizing circuit comprising;
a data buffer coupled to the memory device and having a plurality of data locations at which read data are respectively stored;
a multiplexer coupled to the data buffer to selectively couple read data stored at respective data locations of the data buffer to an output terminal in accordance with a selection signal;
a write pointer circuit coupled to the memory device and the data buffer and adapted to generate a write pointer signal to sequentially select one of the plurality of data locations of the data buffer for storing read data received from the memory device responsive to a strobe signal provided by the memory device;
a read pointer circuit coupled to the multiplexer and adapted to generate responsive to the core clock signal a read pointer signal provided to the multiplexer to sequentially select one of the plurality of data locations of the buffer from which the read data stored therein is coupled to the output terminal of the multiplexer; and
a write-read pointer compare circuit coupled to the write and read pointer circuits to compare the write and read pointer signals and adapted to generate and provide the write-read pointer offset signal indicative of the comparison to the memory controller. - View Dependent Claims (43, 44, 45, 46, 47, 48, 49, 50)
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51. A method of adjusting the timing of retrieving read data from a buffer, the method comprising:
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requesting read data from at least one memory device;
sequentially selecting data locations of the buffer at which read data are stored responsive to a strobe signal provided by the memory device, the currently selected data location at which read data is stored identified by a write pointer incremented responsive to the strobe signal;
sequentially selecting data locations of the buffer from which stored read data is retrieved response to a core clock signal, the currently selected data location from which read data is retrieved identified by a read pointer incremented responsive to the core clock signal;
comparing the write pointer and the read pointer to determine a write-read pointer offset indicative of the relative timing between storing the read data to a data location and retrieving the read data from the data location; and
based on the write-read pointer offset, adjusting the timing of retrieving read data from the buffer relative to the storing of the read data in a data location in the buffer. - View Dependent Claims (52, 53, 54, 55, 56)
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57. A method of adjusting the relative timing between issuing memory write commands and memory read commands, the method comprising:
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storing read data provided by at least one memory device in sequentially selected data locations of a buffer, the data location at which read data are currently stored selected by a write pointer;
retrieving read data stored in the buffer from sequentially selected data locations, the data location from which read data are currently retrieved selected by a read pointer;
generating a write-read pointer offset indicative of a data location offset between the data location selected by the write pointer and the data location selected by the read pointer; and
adjusting the timing between the issuance of memory write commands and memory read commands based on the write-read pointer offset. - View Dependent Claims (58, 59, 60, 61, 62)
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Specification