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System and method for an asynchronous data buffer having buffer write and read pointers

  • US 20050286506A1
  • Filed: 06/04/2004
  • Published: 12/29/2005
  • Est. Priority Date: 06/04/2004
  • Status: Active Grant
First Claim
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1. A read data synchronizing circuit for coupling read data from a memory device operating according to a memory device clock signal to a memory controller operating according to a core clock signal, the read data synchronizing circuit comprising:

  • a data buffer coupled to the memory device and having a plurality of data locations at which read data are respectively stored;

    a multiplexer coupled to the data buffer to selectively couple read data stored at respective data locations of the data buffer to an output terminal in accordance with a selection signal;

    a write pointer circuit coupled to the memory device and the data buffer and adapted to generate a write pointer signal to sequentially select one of the plurality of data locations of the data buffer for storing read data received from the memory device responsive to a strobe signal provided by the memory device;

    a read pointer circuit coupled to the multiplexer and adapted to generate responsive to the core clock signal a read pointer signal provided to the multiplexer to sequentially select one of the plurality of data locations of the buffer from which the read data stored therein is coupled to the output terminal of the multiplexer; and

    a write-read pointer compare circuit coupled to the write and read pointer circuits to compare the write and read pointer signals and adapted to generate a write-read pointer offset signal indicative of the comparison.

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