Method of manufacturing thin film transistor panel

• US 20050287692A1
• Filed: 05/10/2005
• Published: 12/29/2005
• Est. Priority Date: 06/29/2004
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Lee, Yong-Uk, Kim, Bo-Sung
• Granted Patent: US 7,422,916 B2
• Time in Patent Office: Days
• US Class Current: 438/30
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136236 using a grey or half tone lithographic process
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H10K 59/12 Active-matrix OLED [AMOLED] displays

Abstract

A method of manufacturing a thin film transistor panel is provided, which includes forming a first signal line on a substrate. The method also includes forming in sequence a first insulating layer and a semiconductor layer on the first signal line. The method further includes patterning the semiconductor layer and the first insulating layer through one photolithography process to form a patterned semiconductor layer and a patterned first insulating layer. The method also includes forming a second signal line on the patterned semiconductor layer and the patterned first insulating layer.

Claims

1. A method of manufacturing a thin film transistor panel, the method comprising:

forming a first signal line on a substrate;

forming in sequence a first insulating layer and a semiconductor layer on the first signal line;

patterning the semiconductor layer and the first insulating layer through one photolithography process to form a patterned semiconductor layer and a patterned first insulating layer; and

forming a second signal line on the patterned semiconductor layer and the patterned first insulating layer.

2. The method of claim 1, further comprising:

applying a second insulating layer on the second signal line; and

patterning the second insulating layer.

3. The method of claim 2, wherein the second insulating layer is made of organic material.

4. The method of claim 3, wherein a thickness of the first insulating layer is about 2,500 Å

to 5,500 Å

.

5. The method of claim 3, further comprising:

forming a third insulating layer made of inorganic material under the second insulating layer.

6. The method of claim 5, wherein the second and third insulating layers are patterned through one photolithography process.

7. The method of claim 6, wherein the second insulating layer has photosensitivity.

8. The method of claim 7, wherein a difference between a thickness of the second insulating layer before and after the patterning of the second and third insulating layers is about 1,000 Å

to 2,000 Å

.

9. The method of claim 8, wherein a thickness of the first insulating layer is about 2,500 Å

to 5,500 Å

, a thickness of the second insulating layer before the patterning of the second and third insulating layers is about 4,150 Å

to 4,250 Å

, and a thickness of the third insulating layer is about 1,000 Å

to 2,000 Å

.

10. The method of claim 3, further comprising:

forming a first contact hole in the first insulating layer to expose a portion of the first signal line; and

forming a second contact hole in the second insulating layer to expose the portion of the first signal line.

11. The method of claim 10, further comprising forming a third contact hole in the second insulating layer to expose a portion of the second signal line.

12. The method of claim 11, further comprising forming a pixel electrode on the second insulating layer, the pixel electrode being connected with the exposed portion of the second signal line via the third contact hole.

13. The method of claim 11, further comprising forming a contact assistant on the second insulating layer, the contact assistant being connected with the exposed portion of the first signal line via the first and second contact holes.

14. A method of manufacturing a thin film transistor panel, the method comprising:

forming a first signal line on a substrate;

forming in sequence a first insulating layer and a semiconductor layer on the first signal line;

patterning the semiconductor layer and the first insulating layer through one photolithography process to form a patterned semiconductor layer and a patterned first insulating layer, the patterned first insulating layer having a first contact hole to expose a portion of the first signal line;

forming a second signal line on the patterned semiconductor layer and the patterned insulating layer;

applying a second insulating layer on the second signal line; and

patterning the second insulating layer to have a second contact hole at the substantially same location as the first contact hole.

15. The method of claim 14, wherein the patterning of the semiconductor layer and the first insulating layer comprises:

applying a photosensitive layer on the semiconductor layer;

forming the first contact hole by etching the semiconductor layer and the first insulating layer using the photosensitive layer as an etching mask; and

removing the photosensitive layer.

16. The method of claim 14, wherein the patterning of the semiconductor layer and the first insulating layer comprises:

applying a photosensitive layer on the semiconductor layer;

exposing to light the photosensitive layer through a mask having a slit pattern;

developing the photosensitive layer;

forming the first contact hole by etching the semiconductor layer and the first insulating layer using the photosensitive layer as an etching mask; and

removing the photosensitive layer.

17. The method of claim 14, wherein the semiconductor layer has an intrinsic semiconductor layer and an extrinsic semiconductor layer.

18. The method of claim 14, wherein the second insulating layer is made of organic material.

19. The method of claim 15, further comprising applying a third insulating layer made of inorganic material under the second insulating layer.

20. The method of claim 19, further comprising exposing to light the first signal line through the first contact hole by removing the third insulating layer exposed after patterning the second insulating layer.

21. The method of claim 20, wherein the second insulating layer has photosensitivity.

22. The method of claim 21, wherein a difference between a thickness of the second insulating layer before and after the third insulating layer is patterned is about 1,000 Å

to 2,000 Å

.

23. The method of claim 22, wherein a thickness of the first insulating layer is about 2,500 Å

to 5,500 Å

, a thickness of the second insulating layer in the applying step of the second insulating layer is about 4,150 Å

to 4,250 Å

, and a thickness of the third insulating layer is about 1,000 Å

to 2,000 Å

.

24. The method of claim 20, further comprising forming a contact assistant on the second insulating layer, the contact assistant being connected with the exposed portion of the first signal line.

25. The method of claim 14, further comprising forming a pixel electrode on the second insulating layer.