Method for fabricating high aspect ratio MEMS device with integrated circuit on the same substrate using post-CMOS process

• US 20050287760A1
• Filed: 04/22/2005
• Published: 12/29/2005
• Est. Priority Date: 06/29/2004
• Status: Active Grant

• Current Assignee: Peking University
• Original Assignee: Peking University
• Inventors: Zhou, Jian, Zhu, Yong, Wang, Yangyuan, Fan, Jie, Yan, Guizhen, Liu, Xuesong
• Granted Patent: US 7,618,837 B2
• Time in Patent Office: Days
• US Class Current: 438/404
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0728 Pre-CMOS, i.e. forming the micromechanical structure before the CMOS circuit
• CPC Class Codes: H01L 27/0617 comprising components of the field-effect type H01L27/0251 takes precedence

Abstract

The invention discloses a novel flexible, modular fabrication method for integrated high aspect ratio single crystal silicon microstructures designed and manufactured in a post conventional CMOS process (Post-CMOS). The method involves the standard circuits formation, the electrical isolation trenched etching and refilling, backside etching, interconnection formation, and structure releasing. Further, a method of tailoring the trench profile for refill the trench fully without void is also disclosed.

Claims

1. A method for fabricating a high-aspect-ratio device with integrated circuit in the same substrate using post-CMOS process, the method comprising the steps of:

1) fabricating circuits on a first region of a substrate using any of well-known semiconductor circuit fabrication processes;

2) fabricating deep electrical isolation trenches in the substrate using DRIE, refilling electrical isolation dielectric in the trenches, and backside etching the substrate to expose the bottom of trenches to electrically isolate mechanical structures and circuits;

3) fabricating electrical interconnection to electrically connect mechanical structures and circuits;

4) releasing mechanical structures using DRIE technology.

2. The method according to claim 1, wherein the circuits are fabricated firstly using standard CMOS technology without metal connection, after the fabrication of isolation trenches, metal is formed as electrical connection and act as mask of DRIE.

3. The method according to claim 1, wherein the substrate is double side polished single crystal silicon wafer.

4. The method according to claim 1, wherein the device comprises mechanical structures, circuits, and electrical isolation trenches.

5. The method according to claim 1, wherein the formation of circuits is accomplished by using standard CMOS technology.

6. The method according to claim 1, wherein the electrical isolation between circuits and structures are realized by high aspect ratio deep isolation trenches.

7. The method according to claim 1, wherein the electrical interconnection is disposed over the trenches to connect the circuits and the structures.

8. The method according to claim 1, wherein metal layers are used for connecting circuit region and structure region, and acting as a mask to release structures during DRIE.

9. The method according to claim 1, wherein the electrical isolation trench are between the first region of circuit region and the second region of structure.

10. The method according to claim 1, wherein the thickness of the structures is varied depending on applications, and thickness of the electrical isolation trench is changed accordingly, confirming that the electrical isolation trench is a little thicker than the structure.

11. The method according to claim 1, wherein depositing a passivation layer to protect the circuits after the formation of the circuits.

12. The method according to claim 1, wherein photoresist is used as protection layer to protect the circuits during DRIE.

13. A method for electrically isolating structures from each other and from circuits on a wafer, the method comprising the steps of:

1) fabricating high aspect ratio deep silicon trenches by DRIE technology between a first region of the circuits and a second region of the structures;

2) depositing a layer of insulating material to refill the silicon trenches;

3) etching the wafer from backside to expose the bottom of the silicon trenches.

14. The method according to claim 13, wherein the insulating material includes low temperature electrical isolating dielectric.

15. The method according to claim 14, wherein the low temperature electrical isolating dielectric comprises at least one of LPCVD SiO₂, polysilicon, LTO, PECVD SiO₂ and parylene.

16. The method according to claim 13, wherein the backside of the substrate is dry etched by DRIE or wet etched by TMAH or KOH solution.

17. A method for tailoring the trench profile to refill the trench fully, the method comprising the steps of:

1) forming an oxide layer on a single crystal silicon with a pattern, whose width is a little larger than that of the trench;

2) depositing a polysilicon layer on the oxide layer by low temperature deposition process and defining with trench pattern;

3) etching the polysilicon layer and single crystal silicon in turn using the same mask by DRIE;

4) removing the polysilicon layer and oxide layer by DRIE and BOE solution respectively after the mask is removed.

18. The method according to claim 17, wherein the trench pattern is aligned with the pattern on the oxide layer.