Diffusion barrier process for routing polysilicon contacts to a metallization layer

• US 20050287793A1
• Filed: 06/29/2004
• Published: 12/29/2005
• Est. Priority Date: 06/29/2004
• Status: Abandoned Application

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Lindsay, Roger W., Blanchet, Aaron R., Carr, Robert C.
• Application Number:
  US10/881,303
• Publication Number:
  US 20050287793A1
• Time in Patent Office: Days
• US Class Current: 438/629
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Methods and apparatus are described to facilitate forming of polysilicon contact plugs with an improved diffusion barrier that can be formed in conjunction with other process steps. Embodiments of the present invention are formed by recessing the polysilicon plug below the surface of the insulation layer, allowing the depression formed at the interface of the insulating layer and the top of the polysilicon plug to be filled with a diffusion barrier/liner layer before deposition and etching of the metal interconnection layer. This allows the etching of the polysilicon contact plug and deposition of the barrier layer to occur along with other process steps. In an embodiment of the present invention the peripheral metal contact plugs and polysilicon contact plugs of a memory array are deposited with liner material and removed in a series of concurrent process steps.

Claims

1. A portion of an integrated circuit, comprising:

a polysilicon contact plug in contact with a first active area of the integrated circuit and a liner material overlying the polysilicon plug; and

a metal contact in contact with a second active area of the integrated circuit; and

wherein the metal contact and the liner material of the polysilicon contact plug are formed concurrently.

2. The portion of an integrated circuit of claim 1, wherein the liner material and the metal contact each further comprise a first metal layer overlying a conductive barrier layer.

3. The portion of an integrated circuit of claim 1, further comprising:

a metal interconnect line in contact with a surface of the polysilicon contact plug and the metal contact.

4. A method of forming a portion of an integrated circuit, comprising:

forming a dielectric layer overlying a silicon active area of the integrated circuit;

forming a first contact hole in the dielectric layer exposing a first portion of the silicon active area;

forming a polysilicon layer overlying the dielectric layer and contacting the first portion of the silicon active area;

removing a portion of the polysilicon layer to leave a polysilicon plug in the first contact hole, wherein a surface of the polysilicon plug is recessed below a surface of the dielectric layer;

forming a second contact hole in the dielectric layer exposing a second portion of the silicon active area;

forming a conductive layer overlying the dielectric layer and contacting the surface of the polysilicon plug and the second portion of the silicon active area; and

removing a portion of the conductive layer to leave portions of the conductive layer in the second contact hole and in the first contact hole between the surface of the dielectric layer and the surface of the polysilicon plug.

5. The method of claim 4, further comprising:

forming a metal layer overlying the dielectric layer and in contact with the portions of the conductive layer in the second contact hole and the first contact hole; and

patterning the metal layer to define an interconnect line coupling the portion of the conductive layer in the second contact hole to the portion of the conductive layer in the first contact hole.

7. The method of claim 4, wherein forming the conductive layer further comprises:

forming a conductive barrier layer overlying the dielectric layer and contacting the surface of the polysilicon plug and the second portion of the silicon active area; and

forming a first metal layer overlying the conductive barrier layer.

8. The method of claim 7, further comprising:

forming a second metal layer overlying the dielectric layer and in contact with portions of the first metal layer in the second contact hole and the first contact hole; and

patterning the second metal layer to define an interconnect line coupling the portion of the first metal layer in the second contact hole to the portion of the first metal layer in the first contact hole.

9. A method of forming polysilicon and metal contact plugs, comprising:

forming an insulation layer overlying an active area of an integrated circuit;

forming one or more first and second contact holes in the insulation layer;

forming a polysilicon layer over the insulation layer in contact with the active area through the one or more first contact holes;

removing a portion of the polysilicon layer to form one or more polysilicon contact plugs in the one or more contact holes, wherein a top surface of each of the one or more polysilicon contact plugs are formed below a top surface of the insulation layer;

forming a contact liner material layer over the insulation layer in contact with the top surface of each of the one or more polysilicon contact plugs and second contact holes; and

removing a portion of the contact liner material layer to form a diffusion barrier over each polysilicon contact plug in the one or more contact holes and one or more metal contact plugs in the one or more second contact holes.

10. The method of claim 9, further comprising:

forming a metal layer in contact with the diffusion barrier of each contact plug.

11. The method of claim 10, wherein forming a metal layer in contact with the diffusion barrier of each contact plug further comprises masking and etching the metal layer to form one or more metal interconnect lines.

12. The method of claim 10, wherein forming a metal layer in contact with the diffusion barrier of each contact plug further comprises forming a metal layer of one of aluminum, tungsten, and copper.

13. The method of claim 9, wherein forming a contact liner material layer over the insulation layer further comprises forming a contact liner material layer of one of tungsten, titanium, and titanium nitride.

14. The method of claim 9, wherein removing a portion of the contact liner material layer to form a diffusion barrier over each polysilicon contact plug in the one or more contact holes further comprises removing a portion of the contact liner material layer to form diffusion barriers for the one or more polysilicon contact plugs where a top surface of each diffusion barrier is substantially level with the top surface of the insulation layer.

15. A method of fabricating a memory array, comprising:

forming an interlayer dielectric (ILD) isolation stack overlying an active area of memory array;

forming one or more first and second contact holes in the ILD isolation stack;

forming a polysilicon layer over the ILD isolation stack in contact with the silicon active area through the one or more first contact holes;

removing a portion of the polysilicon layer to form one or more polysilicon contact plugs in the one or more first contact holes, wherein a top surface of each of the one or more polysilicon contact plugs are formed below a top surface of the ILD isolation stack;

forming a contact liner material layer over the ILD isolation stack in contact with the top surface of each of the one or more polysilicon contact plugs and the active area through the one or more second contact holes; and

removing a portion of the contact liner material layer to form a diffusion barrier over each polysilicon contact plug in the one or more contact holes and form one or more metal contact plugs in the one or more second contact holes.

16. The method of claim 15, wherein the memory array is a non-volatile memory array.

17. The method of claim 15, further comprising:

forming a metal layer in contact with one or more metal and/or polysilicon contact plugs.

18. The method of claim 17, wherein forming a metal layer in contact one or more metal and/or polysilicon contact plugs further comprises masking and etching the metal layer to form one or more metal interconnect lines.

19. The method of claim 17, wherein forming a metal layer in contact with one or more metal and/or polysilicon contact plugs further comprises forming a metal layer of one of aluminum, tungsten, and copper.

20. The method of claim 15, wherein forming one or more metal contact plugs in the one or more second contact holes further comprises filling the one or more second contact holes with liner material to form one or more metal contact plugs concurrently with the forming the diffusion barriers of the one or more polysilicon contact plugs.

21. The method of claim 15, wherein forming a contact liner material layer over the ILD isolation stack in contact with the top surface of each of the one or more polysilicon contact plugs and the active area through the one or more second contact holes further comprises forming a contact liner material layer of one of tungsten, titanium, and titanium nitride.

22. The method of claim 15, wherein removing a portion of the contact liner material layer to form a diffusion barrier over each polysilicon contact plug in the one or more contact holes and form one or more metal contact plugs in the one or more second contact holes further comprises removing a portion of the contact liner material layer to form diffusion barriers for the polysilicon contact plugs where a top surface of each diffusion barrier is substantially level with the top surface of the ILD isolation stack.

23. A method of forming an integrated circuit, comprising:

forming the active area of a memory array containing a plurality of floating gate memory cells;

forming an insulation layer overlying the active area;

forming one or more first and second contact holes in the insulation layer;

forming a polysilicon layer over the insulation layer in contact with the active area through the one or more first contact holes;

removing a portion of the polysilicon layer to form one or more polysilicon contact plugs in the one or more first contact holes, wherein a top surface of each of the one or more polysilicon contact plugs are formed below a top surface of the insulation layer;

forming one or more metal contact plugs in the one or more second contact holes;

forming a contact liner material layer over the insulation layer in contact with the top surface of each of the one or more polysilicon contact plugs and one or more metal contact plugs; and

removing a portion of the contact liner material layer to form a diffusion barrier over each polysilicon contact plug and metal contact plug.

24. The method of claim 23, wherein the integrated circuit is a memory device.

25. The method of claim 24, wherein the memory device is a non-volatile memory device.

26. The method of claim 23, wherein further comprising:

forming a metal layer in contact with the diffusion barrier of one or more polysilicon and/or metal contact plugs.

27. The method of claim 26, wherein forming a metal layer in contact with the diffusion barrier of one or more polysilicon and/or metal contact plugs further comprises masking and etching the metal layer to form one or more metal interconnect lines.

28. The method of claim 26, wherein forming a metal layer in contact with the diffusion barrier of one or more polysilicon and/or metal contact plugs further comprises forming a metal layer of one of aluminum, tungsten, and copper.

29. The method of claim 23, wherein forming one or more metal contact plugs in the one or more second contact holes further comprises filling the one or more second contact holes with liner material to form one or more metal contact plugs concurrently with the forming the diffusion barriers of the one or more polysilicon contact plugs.

30. The method of claim 23, wherein forming a contact liner material layer over the insulation layer in contact with the top surface of each of the one or more polysilicon contact plugs and one or more metal contact plugs further comprises forming a contact liner material layer of one of tungsten, titanium, and titanium nitride.

31. The method of claim 23, wherein removing a portion of the contact liner material layer to form a diffusion barrier over each polysilicon contact plug in the one or more first contact holes and one or more metal contact plugs further comprises removing a portion of the contact liner material layer to form diffusion barriers for the one or more polysilicon contact plugs where a top surface of each diffusion barrier is substantially level with the top surface of the insulation layer.

32. The method of claim 23, wherein forming one or more first and second contact holes in the insulation layer further comprises:

forming a mask layer overlying the insulation layer;

patterning the mask layer to expose a portion of the insulation layer;

removing a portion of the exposed portion of the insulation layer material to expose the active area; and

removing the mask layer.

33. The method of claim 32, wherein forming a mask layer further comprises forming a mask layer with a photoresist.

34. The method of claim 32, wherein removing the mask layer further comprises stripping the mask layer.

35. The method of claim 32, wherein removing a portion of the exposed portion of the insulation layer material to expose the silicon active area further comprises anisotropically etching the exposed portion of the insulation layer material.

36. A method of forming a Flash memory device, comprising:

forming the silicon active area of a memory array containing a plurality of floating gate memory cells;

forming an interlayer dielectric (ILD) isolation stack overlying the silicon active area;

forming one or more first and second contact holes in the ILD isolation stack;

forming a polysilicon layer over the ILD isolation stack in contact with the silicon active area through the one or more first contact holes;

removing a portion of the polysilicon layer to form one or more polysilicon contact plugs in the one or more first contact holes, wherein a top surface of each of the one or more polysilicon contact plugs are formed below a top surface of the ILD isolation stack;

forming one or more metal contact plugs in the one or more second contact holes;

forming a contact liner material layer over the ILD isolation stack in contact with the top surface of each of the one or more polysilicon and metal contact plugs; and

removing a portion of the contact liner material layer to form a diffusion barrier over the polysilicon and metal contact plugs.

37. The method of claim 36, wherein the Flash memory device is one of a NAND Flash memory device and a NOR Flash memory device.

38. The method of claim 36, wherein further comprising:

forming a metal layer in contact with the diffusion barrier of one or more polysilicon and/or metal contact plugs.

39. The method of claim 38, wherein forming a metal layer in contact with the diffusion barrier of one or more polysilicon and/or metal contact plugs further comprises masking and etching the metal layer to form one or more metal interconnect lines.

40. The method of claim 38, wherein forming a metal layer in contact with the diffusion barrier of one or more polysilicon and/or metal contact plugs further comprises forming a metal layer of one of aluminum, tungsten, and copper.

41. The method of claim 36, wherein forming one or more metal contact plugs further comprises filling the one or more second contact holes with liner material to form one or more metal contact plugs concurrently with the forming the diffusion barriers of the one or more polysilicon contact plugs.

42. The method of claim 36, wherein forming a contact liner material layer over the ILD isolation stack in contact with the top surface of each of the one or more polysilicon and metal contact plugs further comprises forming a contact liner material layer of one of tungsten, titanium, and titanium nitride.

43. The method of claim 36, wherein removing a portion of the contact liner material layer to form a diffusion barrier over the polysilicon and metal contact plugs further comprises removing a portion of the contact liner material layer to form diffusion barriers for the one or more polysilicon contact plugs where a top surface of each diffusion barrier is substantially level with the top surface of the ILD isolation stack.

44. A memory array, comprising:

an array of memory cells;

an interlayer dielectric (ILD) isolation layer placed over the array, wherein the ILD isolation layer has one or more first and second contact holes;

one or more polysilicon contact plugs wherein the polysilicon contact plugs are formed within the one or more first contact holes of the ILD isolation layer, where a top surface of each of the one or more polysilicon contact plugs is positioned below a top surface of the ILD isolation layer, defining one or more depressions;

one or more barrier layers of contact liner material placed in each of the one or more depressions;

one or more metal contact plugs, wherein the metal contact plugs are formed in the one or more second contact holes; and

at least one metal interconnect line in contact with the one or more barrier layers and/or metal contact plugs.

45. The memory array of claim 44, wherein the memory array is a non-volatile memory array.

46. The memory array of claim 45, wherein the non-volatile memory array is one of a NOR architecture Flash memory array, a NAND architecture Flash memory array, a Ferroelectric Random Access Memory (FeRAM) memory array, a Nitride Read Only Memory (NROM) array, and a Magnetoresistive Random Access Memory (MRAM) memory array.

47. The memory array of claim 44, wherein the contact liner material is one of tungsten, titanium, and titanium nitride.

48. The memory array of claim 44, wherein the at least one metal interconnect line is one of a tungsten interconnect line, an aluminum interconnect line, and a copper interconnect line.

49. The memory array of claim 44, wherein the metal contact plugs are formed of contact liner material concurrently with the barrier layers.

50. An integrated circuit, comprising:

a silicon active area;

an insulation layer placed over the active area, wherein the insulation layer has one or more first and second contact holes;

one or more polysilicon contact plugs placed within the one or more first contact holes of the insulation layer, wherein a top surface of each of the one or more polysilicon contact plugs is positioned below a top surface of the insulation layer, defining one or more depressions;

one or more barrier layers of contact liner material, wherein the barrier layers are formed in each of the one or more depressions;

one or more metal contact plugs, wherein the metal contact plugs are formed in the one or more second contact holes; and

at least one metal interconnect line in contact with the one or more barrier layers and/or metal contact plugs.

51. The integrated circuit of claim 50, wherein the integrated circuit is a memory device.

52. The integrated circuit of claim 50, wherein the contact liner material is one of tungsten, titanium, and titanium nitride.

53. The integrated circuit of claim 50, wherein the at least one metal interconnect line is one of a tungsten interconnect line, an aluminum interconnect line, and a copper interconnect line.

54. The integrated circuit of claim 50, wherein the metal contact plugs are formed of contact liner material concurrently with the barrier layers.

55. A memory device, comprising:

an array of memory cells;

an insulation layer placed over the array, wherein the insulation layer has one or more first and second contact holes;

one or more polysilicon contact plugs placed within the one or more first contact holes of the insulation layer, wherein a top surface of each of the one or more polysilicon contact plugs is positioned below a top surface of the insulation layer, defining one or more depressions;

one or more barrier layers of contact liner material, wherein the barrier layers are formed in each of the one or more depressions;

one or more metal contact plugs, wherein the metal contact plugs are formed in the one or more second contact holes; and

at least one metal interconnect line in contact with the one or more barrier layers and/or metal contact plugs.

56. The memory device of claim 55, wherein the memory device is a non-volatile memory device.

57. The memory device of claim 56, wherein the non-volatile memory device is one of a NOR architecture Flash memory device, a NAND architecture Flash memory device, a Ferroelectric Random Access Memory (FeRAM) memory device, a Nitride Read Only Memory (NROM) device, and a Magnetoresistive Random Access Memory (MRAM) memory device.

58. The memory device of claim 55, wherein the contact liner is one of tungsten, titanium, and titanium nitride.

59. The memory device of claim 55, wherein the at least one metal interconnect line is one of a tungsten interconnect line, an aluminum interconnect line and a copper interconnect line.

60. The memory device of claim 55, wherein the metal contact plugs are formed of contact liner material concurrently with the barrier layers.

61. A system, comprising:

a processor coupled to a memory device, wherein the memory device comprises, an array of memory cells;

an interlayer dielectric (ILD) isolation layer placed over the array, wherein the ILD isolation layer has one or more first and second contact holes;

one or more polysilicon contact plugs placed within the one or more first contact holes of the ILD isolation layer, wherein a top surface of each of the one or more polysilicon contact plugs is positioned below a top surface of the ILD isolation layer, defining one or more depressions;

one or more barrier layers of contact liner material, wherein the barrier layers are formed in each of the one or more depressions;

one or more metal contact plugs, wherein the metal contact plugs are formed of contact liner material in the one or more second contact holes concurrently with the one or more barrier layers; and

at least one metal interconnect line in contact with the one or more barrier layers and/or metal contact plugs.

62. The system of claim 61, wherein the memory device is a non-volatile memory device.

63. The system of claim 62, wherein the non-volatile memory device is one of a NOR architecture Flash memory device, a NAND architecture Flash memory device, a Ferroelectric Random Access Memory (FeRAM) memory device, a Nitride Read Only Memory (NROM) device, and a Magnetoresistive Random Access Memory (MRAM) memory device.

64. The system of claim 61, wherein the processor is a memory controller.

65. A memory device, comprising:

an array of memory cells;

an insulation layer placed over the array, wherein the insulation layer has one or more first contact holes;

one or more polysilicon contact plugs placed within the one or more first contact holes of the insulation layer, having a means for defining one or more depressions between a top surface of each of the one or more polysilicon contact plugs and a top surface of the ILD isolation layer;

a means for forming one or more barrier layers of contact liner material in each of the one or more depressions;

a means for forming one or more metal contact plugs, wherein the metal contact plugs are formed in the one or more second contact holes; and

a means for forming at least one metal interconnect line in contact with the one or more barrier layers and/or metal contact plugs.

66. The memory device of claim 65, wherein the memory device is a non-volatile memory device.

67. The memory device of claim 66, wherein the non-volatile memory device is one of a NOR architecture Flash memory device, and a NAND architecture Flash memory device.

68. An integrated circuit, comprising:

a silicon active area;

an insulation layer placed over the active area, wherein the insulation layer has one or more contact holes;

one or more polysilicon contact plugs placed within the one or more contact holes of the insulation layer, wherein a top surface of each of the one or more polysilicon contact plugs is positioned below a top surface of the insulation layer, defining one or more depressions;

one or more barrier layers of contact liner material, wherein the barrier layers are formed in each of the one or more depressions; and

at least one metal interconnect line in contact with the one or more barrier layers and/or metal contact plugs.

69. The integrated circuit of claim 68, wherein the integrated circuit is a memory device.

70. The integrated circuit of claim 68, wherein the contact liner material is one of tungsten, titanium, and titanium nitride.

71. The integrated circuit of claim 68, wherein the at least one metal interconnect line is one of a tungsten interconnect line, an aluminum interconnect line, and a copper interconnect line.

72. The integrated circuit of claim 68, wherein one or more metal contact plugs are formed in the insulation layer in one or more second contact holes, wherein the metal contact plugs are formed concurrently with the one or more polysilicon contact plugs and barrier layers.

73. A method of forming a portion of an integrated circuit, comprising:

forming a dielectric layer overlying a silicon active area of the integrated circuit;

forming a contact hole in the dielectric layer exposing a portion of the silicon active area;

forming a polysilicon layer overlying the dielectric layer and contacting the portion of the silicon active area;

removing a portion of the polysilicon layer to leave a polysilicon plug in the contact hole, wherein a top surface of the polysilicon plug is recessed below a surface of the dielectric layer; and

forming a layer of barrier material overlying the dielectric layer and contacting the surface of the polysilicon plug, filling the formed recess between the top surface of the polysilicon plug and the surface of the dielectric layer; and

removing a portion of the barrier layer to leave portions of the barrier layer in the formed recess of the contact hole between the surface of the dielectric layer and the top surface of the polysilicon plug.

74. The method of claim 73, further comprising:

forming a metal layer overlying the dielectric layer and in contact with the portions of the barrier layer in the contact hole; and

patterning the metal layer to define an interconnect line.

75. The method of claim 73, wherein forming a layer of barrier material overlying the dielectric layer and contacting the surface of the polysilicon plug further comprises:

forming a layer of barrier material of one or more differing material layers overlying the dielectric layer and contacting the surface of the polysilicon plug.

76. A method of forming polysilicon contact plugs, comprising:

forming an insulation layer overlying an active area of an integrated circuit;

forming one or more contact holes in the insulation layer;

forming a polysilicon layer over the insulation layer in contact with the active area through the one or more contact holes;

removing a portion of the polysilicon layer to form one or more polysilicon contact plugs in the one or more contact holes, wherein a top surface of each of the one or more polysilicon contact plugs are formed below a top surface of the insulation layer; and

forming a contact liner material layer over the insulation layer in contact with the top surface of each of the one or more polysilicon contact plugs to form a diffusion barrier over each polysilicon contact plug in the one or more contact holes.

77. The method of claim 76, further comprising:

forming a metal layer in contact with the diffusion barrier of each contact plug.

78. The method of claim 77, wherein forming a metal layer in contact with the diffusion barrier of each contact plug further comprises masking and removing portions of the metal layer and underlying contact liner material layer to form one or more metal interconnect lines.

79. The method of claim 77, wherein forming a metal layer in contact with the diffusion barrier of each contact plug further comprises forming a metal layer of one of aluminum, tungsten, and copper.

80. The method of claim 76, wherein forming a contact liner material layer over the insulation layer further comprises forming a contact liner material layer of one or more of tungsten, titanium, and titanium nitride.