Disk drive system on chip with integrated buffer memory and support for host memory access

• US 20050289262A1
• Filed: 08/19/2004
• Published: 12/29/2005
• Est. Priority Date: 06/23/2004
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Sutardja, Sehat
• Granted Patent: US 7,958,292 B2
• Time in Patent Office: Days
• US Class Current: 710/74
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0676 Magnetic disk device
• CPC Class Codes: G06F 5/12 Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
• CPC Class Codes: G11B 20/10527 Audio or video recording; Data buffering arrangements G11B20/12 - G11B20/18 take precedence
• CPC Class Codes: G11B 2020/10675 aspects of buffer control

Abstract

A circuit for a storage device that communicates with a host device comprises a first high speed interface. A storage controller communicates with the high speed interface. A buffer communicates with the storage controller. The storage device generates storage buffer data during operation. The storage controller is adapted to selectively store the storage buffer data in at least one of the buffer and/or in the host device via the high speed interface. A bridge chip for enterprise applications couples the circuit to an enterprise device.

Claims

1. A circuit for a storage device, comprising:

a first high speed interface;

a storage controller that communicates with said high speed interface; and

a buffer that communicates with said storage controller, wherein said storage device generates storage-related buffer data during operation and wherein said storage controller selectively stores said storage-related buffer data in at least one of said buffer and/or transmits and receives said storage-related buffer data over said high speed interface.

2. The circuit of claim 1 wherein said first high speed interface includes a serial Advanced Technology Attachment (ATA) interface.

3. The circuit of claim 1 further comprising:

a processor that communicates with said storage controller;

a spindle/VCM driver that communicates with said storage controller; and

a read/write channel circuit that communicates with said storage controller.

4. The circuit of claim 3 further comprising a storage assembly that comprises:

a storage medium that stores data;

a spindle motor that rotates said storage medium and that communicates with said spindle/VCM driver;

a read/write arm that reads and writes data to said storage medium and that communicates with said read/write channel circuit.

5. A system comprising the circuit of claim 1 and further comprising a host device that transmits and receives said storage-related buffer data to said storage device.

6. The system of claim 5 wherein said host device includes:

a second high speed interface that communicates with said first high speed interface; and

volatile memory, wherein at least part of said volatile memory stores said storage-related buffer data from said storage device.

7. A system on chip (SOC) comprising said circuit of claim 1.

8. A multi-chip-module (MCM) comprising said circuit of claim 1.

9. A system on chip (SOC) comprising said circuit of claim 3.

10. A multi-chip-module (MCM) comprising said circuit of claim 3.

11. A system comprising:

a host device that includes;

a processor;

volatile memory that communicates with said processor; and

a first high speed interface that communicates with at least one of said processor and/or said volatile memory; and

a storage device that includes;

a second high speed interface that communicates with said first high speed interface;

a storage controller that communicates with said second high speed interface; and

a buffer that communicates with said storage controller, wherein said storage device generates storage-related buffer data during operation and wherein said storage controller is adapted to selectively store said storage-related buffer data in at least one of said buffer and/or in said volatile memory of said host device via said first and second high speed interfaces.

12. The system of claim 11 wherein said first and second high speed interfaces include serial Advanced Technology Attachment (ATA) interfaces.

13. The system of claim 11 wherein said storage device further comprises:

a processor that communicates with said storage controller;

a spindle/VCM driver that communicates with said storage controller; and

a read/write channel circuit that communicates with said storage controller.

14. The system of claim 13 wherein said storage device further comprises a storage assembly that includes:

a storage medium that stores data;

a spindle motor that rotates said storage medium and that communicates with said spindle/VCM driver; and

a read/write arm that reads and writes data to said storage medium and that communicates with said read/write channel circuit.

15. The system of claim 11 wherein said storage device is implemented as a system on chip.

16. The system of claim 11 wherein said storage device is implemented as a multi-chip-module.

17. The system of claim 13 wherein said storage device is implemented as a system on chip.

18. The system of claim 13 wherein said storage device is implemented as a multi-chip-module.

19. A bridge circuit, comprising:

a first interface that provides a serial Advanced Technology Attachment (ATA) interface;

a second interface that provides one of a serial attached SCSI (SAS) or Fiber Channel (FC) interface;

a processor that communicates with said first and second interfaces and that supports interface and data processing; and

memory that communicates with said processor.

20. The bridge circuit of claim 19 wherein said first and second interfaces and said processor are implemented as an integrated circuit.

21. The bridge circuit of claim 20 wherein said integrated circuit further comprises said memory.

22. A system comprising the bridge circuit of claim 19 and further comprising a storage device that communicates with said first interface of said bridge circuit.

23. The system of claim 22 wherein said storage device comprises:

a third interface that provides a serial Advanced Technology Attachment (ATA) interface and that communicates with said first interface; and

a storage controller that communicates with said third interface.

24. The system of claim 23 wherein said storage device generates storage-related buffer data during operation and wherein said storage controller stores said storage-related buffer data in said bridge circuit via said third and first interfaces.

25. The system of claim 23 wherein said storage device further comprises:

a second processor that communicates with said storage controller and that provides spindle/VCM control; and

a read/write channel circuit that communicates with said storage controller.

26. The system of claim 25 further comprising a storage assembly that comprises:

a storage medium that stores data;

a spindle motor that rotates said storage medium and that communicates with said second processor;

a read/write arm that reads data from and writes data to said storage medium and that communicates with said read/write channel circuit.

27. A system comprising the bridge circuit of claim 19 and further comprising an enterprise device including a fourth interface that communicates with said second interface and that provides said at least one of a serial attached SCSI (SAS) and/or Fiber Channel (FC) interface.

28. The system of claim 23 wherein said storage device is implemented as a system on chip (SOC).

29. The system of claim 23 wherein said storage device is implemented as a multi-chip-module (MCM).

30. The system of claim 23 wherein said storage device comprises buffer and wherein said storage-related buffer data is selectively stored in at least one of said buffer of said storage device and/or said bridge circuit.

31. A circuit for a storage device that communicates with an external device, comprising:

a first interface that provides a serial Advanced Technology Attachment (ATA) interface;

a processor that performs spindle/VCM and data processing; and

a storage controller that communicates with said first interface and said processor,

wherein said storage device generates storage-related buffer data during operation and wherein said storage controller stores said storage-related buffer data in the external device via said second high speed interface.

32. The circuit of claim 31 further comprising memory that communicates with said storage controller, wherein said storage-related buffer data is selectively stored in at least one of said memory and/or the external device.

33. The circuit of claim 31 further comprising a read/write channel circuit that communicates with said storage controller.

34. The circuit of claim 33 further comprising a hard drive assembly that comprises:

a storage medium that stores data;

a spindle motor that rotates said storage medium and that communicates with said processor;

a read/write arm that reads and writes data to said storage medium and that communicates with said read/write channel circuit.

35. A system comprising the circuit of claim 31 and further comprising a bridge chip including a second interface that provides a serial Advanced Technology Attachment (ATA) interface and that communicates with said first interface and a third interface that provides said one of said serial attached SCSI (SAS) or said Fiber Channel (FC) interface.

36. The system of claim 35 further comprising an enterprise device including a fourth interface that communicates with said third interface.

37. The system of claim 35 wherein said bridge chip further comprises a processor that communicates with said third and fourth interfaces and that performs interface and data processing.

38. The system of claim 37 wherein said bridge chip communicates with memory, wherein said memory stores said storage-related buffer data from said storage device.

39. A system on chip (SOC) comprising said circuit of claim 31.

40. A multi-chip-module (MCM) comprising said circuit of claim 31.

41. A circuit for a storage device, comprising:

first interface means for providing a high speed interface;

storage control means that communicates with said first interface means for controlling storage of data; and

buffer means that communicates with said storage control means for storing buffer data, wherein said storage device generates storage-related buffer data during operation and wherein said storage control means selectively stores said storage-related buffer data in at least one of said buffer means and/or transmits and receives said storage-related buffer data over said first interface means.

42. The circuit of claim 41 wherein said first interface means includes a serial Advanced Technology Attachment (ATA) interface.

43. The circuit of claim 41 further comprising:

processing means for processing data and that communicates with said storage control means;

driver means for generating spindle/VCM signals and that communicates with said storage control means; and

read/write channel means for communicating with said storage control means.

44. The circuit of claim 43 further comprising a storage assembly that comprises:

storing means for storing data;

rotating means for rotating said storing means and that communicates with said driver means; and

read/write means for reading and writing data to said storing means and that communicates with said read/write channel means.

45. A system comprising the circuit of claim 41 and further comprising a host device that stores said storage-related buffer data.

46. The system of claim 45 wherein said host device includes:

second interface means for providing a high speed interface and that communicates with said first interface means; and

volatile storing means for storing data, wherein at least part of said volatile storing means stores said storage-related buffer data from said storage device.

47. A system on chip (SOC) comprising said circuit of claim 41.

48. A multi-chip-module (MCM) comprising said circuit of claim 41.

49. A system on chip (SOC) comprising said circuit of claim 43.

50. A multi-chip-module (MCM) comprising said circuit of claim 43.

51. A system comprising:

a host device that includes;

processing means for processing data;

volatile storing means for storing data and that communicates with said processing means; and

first interface means for providing a high speed interface and that communicates with at least one of said processing means and/or said volatile storing means; and

a storage device that includes;

second interface means for providing a high speed interface and that communicates with said first interface means;

storage control means for controlling storage of data and that communicates with said second interface means; and

buffer means for storing data and that communicates with said storage control means, wherein said storage device generates storage-related buffer data during operation and wherein said storage control means is adapted to selectively store said storage-related buffer data in at least one of said buffer means and/or in said host device via said first and second interface means.

52. The system of claim 51 wherein said first and second interface means include serial Advanced Technology Attachment (ATA) interfaces.

53. The system of claim 51 wherein said storage device further comprises:

processing means for processing data and that communicates with said storage control means;

driver means for generating spindle/VCM signals and that communicates with said storage control means; and

read/write channel means for communicating with said storage control means.

54. The system of claim 53 wherein said storage device further comprises a storage assembly that includes:

storing means for storing data;

rotating means for rotating said storing means and that communicates with said driver means; and

read/write means for reading and writing data to said storing means and that communicates with said read/write channel means.

55. The system of claim 51 wherein said circuit is implemented as a system on chip.

56. The system of claim 51 wherein said storage device is implemented as a multi-chip-module.

57. The system of claim 53 wherein said storage device is implemented as a system on chip.

58. The system of claim 53 wherein said storage device is implemented as a multi-chip-module.

59. A bridge circuit, comprising:

first interface means for providing a serial Advanced Technology Attachment (ATA) interface;

second interface means for providing one of a serial attached SCSI (SAS) or Fiber Channel (FC) interface;

processing means for processing data and that communicates with said first and second interface means and that supports interface and data processing; and

storing means for storing data and that communicates with said processing means.

60. The bridge circuit of claim 59 wherein said first and second interface means and said processing means are implemented as an integrated circuit.

61. The bridge circuit of claim 60 wherein said integrated circuit further comprises said storing means.

62. A system comprising the bridge circuit of claim 59 and further comprising a storage device that communicates with said bridge circuit.

63. The system of claim 62 wherein the storage device comprises:

third interface means for providing a serial Advanced Technology Attachment (ATA) interface and that communicates with said first interface means; and

storage control means for controlling data storage and that communicates with said third interface means.

64. The system of claim 63 wherein said storage device generates storage-related buffer data during operation and wherein said storage control means stores said storage-related buffer data in said bridge circuit via said third and first interface means.

65. The system of claim 63 further comprising:

second processing means that communicates with said storage control means and for providing spindle/VCM control; and

read/write channel means for communicating with said storage control means.

66. The system of claim 65 further comprising a storage assembly that comprises:

storing means for storing data;

rotating means for rotating said storing means and that communicates with said second processing means; and

read/write means for reading and writing data to said storing means and that communicates with said read/write channel means.

67. A system comprising the storage device of claim 59 and further comprising an enterprise device including fourth interface means that communicates with said second interface means for providing said at least one of a serial attached SCSI (SAS) and/or Fiber Channel (FC) interface.

68. The system of claim 62 wherein said storage device is implemented as a system on chip (SOC).

69. The system of claim 62 wherein said storage device is implemented as a multi-chip-module (MCM).

70. The system of claim 63 wherein said storage device comprises storing means for storing data and wherein said storage-related buffer data is selectively stored in at least one of said storing means of said storage device and/or said bridge circuit.

71. A circuit for a storage device that communicates with an external device, comprising:

first interface means for providing a serial Advanced Technology Attachment (ATA) interface;

processing means for performing spindle/VCM and data processing; and

storage control means for controlling data storage and that communicates with said first interface means and said processing means,

wherein said storage device generates storage-related buffer data during operation and wherein said storage control means stores said storage-related buffer data in the external device via said second high speed interface means.

72. The circuit of claim 71 further comprising buffer means for storing data and that communicates with said storage control means, wherein said storage-related buffer data is selectively stored in at least one of said buffer means and/or the external device.

73. The circuit of claim 71 further comprising read/write channel means for communicating with said storage control means.

74. The circuit of claim 73 further comprising a storage assembly that comprises:

storing means for storing data;

rotating means for rotating said storing means; and

read/write means for reading data from and writing data to said storing means and that communicates with said read/write channel means.

75. The system comprising the circuit of claim 71 and further comprising a bridge chip including a second interface means for providing a serial Advanced Technology Attachment (ATA) interface and that communicates with said first interface means and third interface means for providing said one of said serial attached SCSI (SAS) or said Fiber Channel (FC) interface.

76. The system of claim 75 further comprising an enterprise device including fourth interface means for communicating with said third interface means.

77. The system of claim 75 wherein said bridge chip further comprises processing means that communicates with said third and fourth interface means for performing interface and data processing.

78. The system of claim 77 wherein said bridge chip communicates with buffer storing means for storing said storage-related buffer data from said storage device.

79. A system on chip (SOC) comprising said circuit of claim 71.

80. A multi-chip-module (MCM) comprising said circuit of claim 71.

81. A method for operating a storage device that communicates with a host device, comprising:

providing a high speed interface between the storage device having a local buffer and the host device;

generating storage-related buffer data during operation;

selectively storing said storage-related buffer data in said local buffer or transmitting and receiving said storage-related buffer data over said high speed interface to/from said host device.

82. The method of claim 81 wherein said high speed interface includes a serial Advanced Technology Attachment (ATA) interface.

83. The method of claim 81 further comprising using volatile storage associated with the host device for storing said storage-related buffer data.

84. A method for utilizing a storage control system in multiple applications, comprising:

producing a plurality of storage control systems that have a common design and that include a storage controller and a local buffer;

selectively enabling host-based buffering of buffer data, which is generated during operation of said storage control system, over a high speed interface with a host device;

using at least one of said storage control systems in a first application wherein said host-based buffering is disabled and said local buffer is used to store said buffer data; and

using at least one of said storage control systems in a second application wherein said host-based buffering of data is enabled.

85. The method of claim 84 further comprising using a high speed interface to communicate buffer data between said storage control system and said host device.

86. The method of claim 85 wherein said high speed interface is a serial Advanced Technology Attachment (ATA) interface.

87. The method of claim 84 wherein said local buffer stores between 4 MB and less than 64 MB of data.

88. The method of claim 87 wherein said local buffer stores 16 MB of data.

89. The method of claim 84 further comprising implementing said storage control system and said local buffer as a system on chip (SOC).

90. The method of claim 89 further comprising omitting pins on said SOC for connecting external memory.

91. The method of claim 84 further comprising implementing said storage control system and said local buffer as a multi-chip module.

92. The method of claim 84 wherein said storage system is a hard disk drive (HDD) control system.