Device and method for interoperability instruction set

• US 20050289264A1
• Filed: 06/08/2005
• Published: 12/29/2005
• Est. Priority Date: 06/08/2004
• Status: Abandoned Application

• Current Assignee: Covia Labs, Inc.
• Original Assignee: Covia Labs, Inc.
• Inventors: Bernstein, Bruce, Mirabella, Richard, Pieb, Wolfgang, Illowsky, Daniel, Wenocur, Michael, Tiberi, Richard, Sidney, Raymond
• Application Number:
  US11/148,977
• Publication Number:
  US 20050289264A1
• Time in Patent Office: Days
• US Class Current: 710/104
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 11/2082 Data synchronisation
• CPC Class Codes: G06F 16/2365 Ensuring data consistency and integrity
• CPC Class Codes: G06F 21/445 by mutual authentication, e.g. between devices or programs
• CPC Class Codes: G06F 21/6218 to a system of files or objects, e.g. local or distributed file system or database
• CPC Class Codes: G06F 2209/5015 Service provider selection
• CPC Class Codes: G06F 2221/2113 Multi-level security, e.g. mandatory access control
• CPC Class Codes: G06F 2221/2149 Restricted operating environment
• CPC Class Codes: G06F 8/10 Requirements analysis; Specification techniques
• CPC Class Codes: G06F 8/20 Software design
• CPC Class Codes: G06F 8/24 Object-oriented
• CPC Class Codes: G06F 8/30 Creation or generation of source code
• CPC Class Codes: G06F 8/41 Compilation
• CPC Class Codes: G06F 8/61 Installation
• CPC Class Codes: G06F 8/63 Image based installation; Cloning; Build to order
• CPC Class Codes: G06F 8/658 Incremental updates; Differential updates
• CPC Class Codes: G06F 8/71 Version control security arrangements therefor G06F21/57; Configuration management
• CPC Class Codes: G06F 9/449 Object-oriented method invocation or resolution
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system
• CPC Class Codes: G06F 9/5011 the resources being hardware resources other than CPUs, Servers and Terminals
• CPC Class Codes: G06F 9/5027 : the resource being a machine, e.g. CPUs, Servers, Terminals
• CPC Class Codes: G06F 9/5044 : considering hardware capabilities
• CPC Class Codes: G06F 9/5072 : Grid computing
• CPC Class Codes: G06F 9/54 : Interprogram communication
• CPC Class Codes: G06F 9/541 : via adapters, e.g. between incompatible applications
• CPC Class Codes: G06F 9/542 : Event management; Broadcasting; Multicasting; Notifications
• CPC Class Codes: H04L 65/1083 : In-session procedures
• CPC Class Codes: H04L 65/1094 : Inter-user-equipment sessions transfer or sharing
• CPC Class Codes: H04L 65/80 : Responding to QoS
• CPC Class Codes: H04L 67/10 : in which an application is distributed across nodes in the network software deployment G06F8/60; multiprogramming arrangements G06F9/46
• CPC Class Codes: H04L 67/104 : Peer-to-peer [P2P] networks
• CPC Class Codes: H04L 67/1068 : Discovery involving direct consultation or announcement among potential requesting and potential source peers
• CPC Class Codes: H04L 67/1072 : Discovery involving ranked list compilation of candidate peers
• CPC Class Codes: H04L 67/1095 : Replication or mirroring of data, e.g. scheduling or transport for data synchronisation between network nodes
• CPC Class Codes: H04L 67/14 : Session management for real-time applications in data packet communications networks H04L65/1066
• CPC Class Codes: H04L 67/51 : Discovery or management thereof, e.g. service location protocol [SLP] or web services
• CPC Class Codes: H04L 69/08 : Protocols for interworking; Protocol conversion
• CPC Class Codes: H04L 69/24 : Negotiation of communication capabilities
• CPC Class Codes: H04L 69/328 : in the presentation layer [OSI layer 6]
• CPC Class Codes: H04N 21/41265 : having a remote control device for bidirectional communication between the remote control device and client device unidirectional remote control device H04N21/42204
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/00 : Reducing energy consumption in communication networks

Abstract

System, device, method, and computer program and computer program products for providing communicating between devices having similar or dissimilar characteristics and facilitating seamless interoperability between them. Computer program software and methods of and systems and devices for sharing of content, applications, resources and control across similar and dissimilar permanently or intermittently connected electronic devices. Devices, systems, appliances, and the like communicating and/or interoperating within the framework provided. An interoperability instruction set may be used to represent the code portions of a Dart. A Dart Engine executes these instructions. Interoperability instruction set may include instructions to enhance the speed of operations, carry-out interoperability methodologies and expose the capabilities and content of devices to each other. Include instructions for exposing and the use of unique capabilities and content of devices to other device even when the other devices have no prior knowledge of the unique capabilities and content.

Claims

1. An apparatus for effecting an interoperability instruction set (IIS), the apparatus comprising:

a processor, a memory coupled to the processor, and an input/output (I/O) interface to support communications with the processor by an entity external to the apparatus;

execution supportive interoperability means for carrying-out methodologies involving at least one of recruitment, renditioning, creationism, vertical layering, linear-tasking, social synchronization, and social security; and

communications interoperability instructions for opening and maintaining a communication session and the procedures, data, content or other information that goes between communicating devices during the communication session.

2. An apparatus as in claim 1, wherein:

the execution supportive interoperability means comprises interoperability instructions for carrying-out the methodologies.

3. An apparatus as in claim 1, wherein one or more of the following are true:

recruitment comprises recruiting a team of devices by a recruitment procedure including;

(a) sending, from an initiating source device, an inspection procedure operative to find a device having a needed resource or capability to at least one reachable device different from the initiating source device over at least one communication link, the inspection procedure including inspection procedure instructions coded in an executable form common to both the initiating source device and to device the inspection procedure is intended to reach;

(b) receiving and executing the received inspection procedure on each of the reachable devices to identify if there is at least one resource or capability of the reachable device needed by the initiating source device;

(c) sending a return to the initiating source device at least when the reachable device has access to a resource or capability identified as being needed by the initiating source device;

(d) receiving the return from each of the reachable devices directly or indirectly over the communication link;

(e) analyzing, by an application executing on the initiating device, the received returns from all responding reachable devices to determine a utilization plan identifying the combination of capabilities and resources of the initiating source device and the responding reachable devices to best carry out the intent of the application; and

(f) distributing, by an application program executing on the initiating device, at least one of executable code, data, content, and/or Dart to at least one of each of the reachable devices identified as having a needed resource or capability according to the identified utilization plan; and

renditioning including the segmenting of a software application into a set of separately executable images by a procedure comprising;

(a) separating the devices to be encountered into classes according to their possible resources and capabilities for carrying out one or more aspects of the intent of the application;

(b) separating the environment or operating requirements likely to be encountered into classes according to the needs for distinct rendering or other runtime requirements for carrying out one or more aspects of the intent of the application;

(c) specifying the data, code, content and other digitally representable resources needed for an executable image needed to be able to carry out one or more aspects of the intent of the application on each class of device and each environment or operating requirement;

(d) generating a utilization plan for choosing which devices and corresponding individually assigned executable images are to be run on each device to be used to carry out the intent of the application given a list of candidate devices, their resources and capabilities, and the required or desired environment or operating parameters; and

(e) specifying the data, code, content and other digitally representable resources needed to implement and carry out the utilization plan on each class of device and each environment or operating requirement; and

creationism comprises a creationism procedure enabling an initial individually executable image or package of individually executable images to dynamically generate at least one other target individually executable data image or package of individually executable data images to carry out the intent of the initial executable image or package of individually executable images, the creationism procedure further comprising;

(a) collecting first information about at least one of the characteristics, content, resources, or capabilities of devices and or other environments for execution of generated executable images or packages of images which might be of use in carrying out the intent or part of the intent of the generating executable image or package;

(b) determining how to assemble at least one of;

(i) parts of its own image, (ii) collected information, or (iii) programmatically generated information, to make efficient use of the resources, capabilities and content of the target devices or environments for which information was collected; and

(c) gathering second information necessary to generate one or more other independently generated executable data images or image packages as needed to carry out the intent of the generated target executable image or image package in an unlimited sequence; and

vertical layering comprises performing an event driven vertical layering procedure for coordinating the operations of and data movement between procedural components within or between one or more teamed devices, the event driven vertical layering procedure comprising;

(a) defining or generating a static event data structure whose fields and field semantics are generally known and understood between all the event generating and processing units across one or more devices and the procedural components running in the one or more devices;

(b) defining or generating a queue on each teamed device which stores, removes, manages, and controls access to the event data structure instances;

(c) managing the placing, modification, and removing of events on the queue accessible from all the cooperating procedural components;

(d) specifying and maintaining a common list of event types which are to be serialized and synchronized between the queues of the cooperating devices; and

(e) ensuring that all the events of any of the types on the common list are processed by the procedural components in the exact same order on all devices regardless of what procedural components initiated the events, or which of the teamed devices the procedural components that initiated the events are running on; and

liner tasking providing a procedure of linear tasking for ordering and managing event driven execution and runtimes of a plurality of event processing units of a software application package, the procedure including;

(a) providing a software object oriented framework which includes a base event processing unit class, and zero or more event processing unit classes which inherit either directly or indirectly from the base event processing unit class;

(b) creating, maintaining, adding, deleting or reordering links that form a graph or topology of event processing units in a manner that ensures that there is always a single linear deterministic ordering for passing events through the graph of processing units formed by the links; and

(c) dynamically changing the graph or topology of processing units according to the needs of the running application;

social synchronization comprises a procedure for maintaining synchronization of resources across one or more dynamically created teams of homogeneous and/or heterogeneous devices which can be intermittently directly connected and/or can be indirectly connected through a sequence of direct connections which themselves can be independently intermittently made between other teamed devices, the social synchronization procedure further comprising;

(a) running on an interoperability device an initiating interoperability application program package of one or more independently executable images which logically or physically encapsulates the resource or resources to be synchronized and/or includes all the capabilities needed to collect and manage the resources to be synchronized; and

(b) teaming of other devices by the initiating interoperability application program wherein a possibly intermittent connection is made to other devices and the initiating application spreads interoperability information to the newly teamed devices; and

social security including performing a procedure for automatically, or under other control, and transitively spreading access rights and credentials between interoperability devices, the social security procedure further comprising;

(a) assigning to each interoperability device a unique id;

(b) assigning to each interoperability device an initial set of access rights;

(c) assigning to each interoperability software package one or more unique ids and embedding in the package the sets of unique ids and associated access rights needed by all and or each of the independently executable images that are part of the application package; and

(d) when two interoperability devices open a communication channel any existing access rights for device teams or applications associated with unique ids that are no more restrictive than those existing for the interoperability of the two devices on either device are synchronized with those on the other device.

4. The apparatus of claim 1, wherein the instruction set includes one or more of the Dart instructions selected from the set consisting of BUILTIN_INSTRUCTION, OEM_BUILTIN_INSTRUCTION, PROFILE_INSTRUCTION, and SAVE_INSTRUCTION.

5. The apparatus of claim 1, wherein the Interoperability Instruction Set is the DartInstructionSet and is carried out by an Interoperability Engine.

6. The apparatus of claim 5, wherein the Interoperability Engine is a DartEngine.

7. The apparatus of claim 1, wherein the instruction set is embodied in one or more of:

(1) a software product running on a processor with a different native instruction set, whether the native instruction set is embodied in hardware, software, firmware, microcode, hardware logic or any combination thereof;

(2) firmware, or microcode coordinating and directing the activities of hardware logic units;

(3) hardware logic; and

(4) any combination of these.

8. The apparatus in claim 1, further comprising:

common user interface (UI) interoperability means for manipulating text, symbolic information, and images.

9. The apparatus in claim 8, wherein:

the common user interface interoperability means comprise common user interface interoperability instructions; and

the user interface interoperability instructions include instructions for at least one of decoding, encoding, compressing and decompressing and manipulating and rendering pictures, bitmaps, sounds, input events, text, symbols, audio/video, or other digitally encoded entity, and any combination of one or more of these.

10. The apparatus in claim 1, further comprising:

a processor or CPU, memory coupled to the processor or CPU, and an input/output (I/O) interface being operable to support communications with the processor by an entity external to the apparatus.

11. The apparatus in claim 1, further comprising:

an operating environment associated with the processor, memory, and input/output interface for performing memory access, computation, test and branch, and input/output instructions at least for carrying out general purpose computing tasks.

12. The apparatus in claim 1, further comprising:

device performance enhancing interoperability means used to extend the practical reach of common binary applications and renditions to lower performance devices because the instructions are implemented and executed in the native code format of a physical processor or CPU of the device as part of the engine, rather then by a sequence of slower executing emulated instructions of the application program used for binary compatibility.

13. The apparatus of claim 12, wherein the performance enhancing interoperability means include instructions for one or more of the following:

CPU intensive cryptographic operations on large numbers including one or more of multiplication, division, addition, subtraction, exponentiation, modular exponentiation, hashing, random number generation, digital signature generation and verification, key pair generation, the encoding and decoding of data to be secured or read, and any instruction or set of instructions performing a combination of any two or more of these.

14. The apparatus of claim 13, wherein the processor or CPU intensive cryptographic operations on large numbers include operations involving individual numbers that must be stored in multiple memory words to assure that the values can be accurately and precisely represented and or to ensure a proper degree of security.

15. The apparatus of claim 12, wherein the performance enhancing interoperability means are for performing one or more of the following CPU intensive graphics operations:

bitmap copying, bitmap scaling, bitmap stretching, bitmap transposing, bitmap blending, bitmap filling, curve generation, line generation, circle generation, polygon rendering, piecewise linear curve generation or rendering, hit detection, font character generation and placement, and any combination of these.

16. The apparatus of claim 12, wherein the performance enhancing interoperability means are for performing one or more of the following CPU intensive text or symbol processing operations:

XML parsing, text searching, text insertion, text deletion, text database operations, text-to-text representation conversions, text manipulation, text-to-symbol manipulation, symbol-to-symbol manipulation, and any combination of these.

17. The apparatus of claim 12, wherein the performance enhancing interoperability means are for performing one or more of the following CPU intensive media processing operations:

audio decompression, video decompression, picture decompression, dataset decompression, audio compression, video compression, picture compression, dataset compression, digital image processing, digital audio processing, dataset processing, database operations and any combination of these.

18. The apparatus in claim 1, further comprising:

capabilities exposing interoperability means for exposing any characteristics and functions, including any unique capabilities and functions, of a particular device to software and/or firmware applications and other devices that are being teamed or have been teamed through the use of the recruitment procedure or methodology.

19. The apparatus in claim 1, further comprising:

security maintenance interoperability instructions for accessing and setting or resetting of;

security features, grouping of devices with a particular set of cross device access rights, and access rights for applications to devices and resources.

20. The apparatus in claim 1, further comprising:

containment interoperability means allow separately generated Darts or executable procedures, to dynamically become part of the linear tasking based runtime environment of other Darts or executable procedures, whether as a child that inherits its environment from its parent or as a parent which provides its runtime environment to any child, or where the generated Dart or executable procedure serve as both parent and child of other executable procedures.

21. The apparatus in claim 1, further comprising:

containment (DartContainment) interoperability instructions to allow separately generated Darts, whether generated by one or more DartTools or by Dart Creationism, to dynamically become part of the Linear Tasking based DartRuntime of other Darts, whether as a child Dart that inherits its environment from its parent Dart or as a parent Dart which provides its runtime environment to any child Darts, or where the generated Darts serve as both parent and child of other Darts.

22. The apparatus in claim 1, wherein:

Darts effectively extend the execution of an originating Dart across other separately generated Darts that are collected, maintained and/or run as part of the operation of the originating Dart.

23. The apparatus in claim 1, further comprising:

storage interoperability instruction means for accessing digital data storage devices and optionally including any one or more of hard disk drives, battery backed up memory, flash storage devices, or other devices which can preserve data while the main power is removed or turned off on the device.

24. The apparatus in claim 1, further comprising:

compatibility interoperability means (instructions) for signaling, retiring and otherwise managing DartEvents or events and an event queue (EventQueue) or DartEventQueue which drives asynchronous and or synchronous processing of a Dart executing across one or more devices.

25. The apparatus in claim 1, further comprising:

unique capabilities instructions to expose any characteristics and functions of a particular device to software applications and other devices.

26. The apparatus in claim 25, wherein the unique capabilities instructions may include an instruction selected from the set of instructions consisting of:

a Dart PROFILE_INSTRUCTION that takes one or more IDs for a resource or capability and returns a value, structured values, or a list of structured values.

27. The apparatus in claim 26, wherein the ID may be just a scalar value pre-assigned to indicate a particular resource or capability, or a major scalar value indicating the general category plus a scalar minor value, or the ID may contain a plurality of scalar values containing any combination of a manufacturer id, major category and minor category.

28. The apparatus in claim 27, wherein one of the major scalar values is a manufacturer ID scalar value that is assigned with a single unique value for every different manufacturer and used to separate the ID values so those specific to a manufacturer can not conflict with those specific to a different other manufacturers'"'"' IDs for resources or capabilities.

29. The apparatus in claim 25, wherein the unique capabilities instructions include an original equipment manufacturer OEM instruction which takes as a parameter a manufacturer ID scalar value, a parameter block specifying the operation to be performed and all the parameters needed to carry out a particular unique application program interface to the unique capabilities.

30. The apparatus in claim 25, wherein the original equipment manufacturer (OEM) instruction comprises a Dart OEM_BUILTIN_INSTRUCTION instruction.

31. The apparatus in claim 27, wherein any other instructions that are part of any non-Dart interoperability instruction set is used to expose unique resources and capabilities of a device through a manufacturer specified application program interface.

32. The apparatus in claim 31, further comprising other instructions that are part of any non-Dart interoperability instruction set performs and or is used to expose unique resources and capabilities of a device, that operate analogously to the Dart PROFILE_INSTRUCTION and the Dart OEM_BUILTIN_INSTRUCTION instruction.

33. The apparatus in claim 31, further comprising an instruction set creating a common procedural environment across homogeneous and heterogeneous devices, the instruction set comprising:

a plurality of instructions designed and optimized to perform all necessary interoperability operations between and among any of a plurality of homogeneous and heterogeneous devices; and

the instructions being dispatched to functions which are compiled or assembled into the native code of the processor of the destination device.

45. The apparatus of claim 1, wherein the instruction set includes instructions used to access to a file system that supports traditional hard files and one or more of the following types of files in any combination:

(i) a memory file;

(ii) a subfile file;

(iii) a part subfile file;

(iv) a part descriptor overriding file; and

(v) any combination or sequential or non-sequential layering of these types of files.

46. The apparatus of claim 45, wherein the memory file is a virtualized a traditional hardfile accessible through the same methods for accessing a hardfile but where the data is kept in changeable main memory of a processor rather than on traditional hard storage such as a hard disk drive or other physical device other than the type commonly used for main memory access of processors.

47. The apparatus of claim 45, wherein the subfile file is a virtualized file representing a linear contiguous range of data inside another file, and where the linear contiguous range is virtualized as beginning at a logical offset of zero, before which there is no data, and the end of the range is bounded by the offset representing the length of the range of data, at and beyond which there is no data.

48. The apparatus of claim 45, wherein the part subfile file is a subfile which represents a logical individually addressable part inside a file holding an application package of one or more independently executable images.

49. The apparatus of claim 45, wherein the part descriptor overriding file, where it exists with the same identifier value as does a specific part, will serve to override any or existing data which once represented the part, whether the existing data is inside a file holding an application package of one or more independently executable images or it is inside any other separate file.

50. The apparatus of claim 49, wherein the part descriptor overriding file is used to logically replace old data for a part without the need to change the existing data inside other files.

51. The apparatus of claim 49, wherein the part descriptor overriding file can represent the data for a part as being one of:

logically deleted or non-existent;

physically stored elsewhere or in another file as identified in the descriptor overriding file;

representative of the access rights or allowed usage of the part data; and

represented inside the descriptor file itself.

34. An interoperability instruction set creating a common procedural environment across homogeneous and heterogeneous devices, the instruction set comprising:

a plurality of instructions designed and optimized to perform all necessary interoperability operations between and among any of a plurality of homogeneous and heterogeneous devices; and

the instructions being dispatched to functions which are compiled or assembled into the native code of the processor of the destination device.

35. An interoperability instruction set as in claim 34, wherein the interoperability instruction set comprises the Dart instruction set as implemented in the DartEngine of a DartPlayer running on one or more DartDevices.

36. An interoperability instruction set as in claim 34, wherein the interoperability instruction set executes in a portable engine creating a common procedural environment in the devices for executing at least one of a device resource and capability recruitment application and another application unmodified to execute on the dissimilar heterogeneous device.

37. An interoperability instruction set as in claim 34, wherein the interoperability instruction set includes at least one and any combination of the following instructions:

recruitment instructions, profile instructions, synchronizing instructions, user interface (ui) and graphics instructions, power management instructions, connection and session management instructions, storage instructions, rendition instructions, creationism instructions, and application parts management instructions.

38. An interoperability instruction set as in claim 34, wherein the addressing field or fields of the instruction can reference at least:

(1) a registers address space, whether or not disjoint from the other address spaces;

(2) a main data address space, whether or not disjoint from the other address spaces;

(3) a stack address space, whether or not disjoint from the other address spaces; and

(4) an application heap address space, whether or not disjoint from the other address spaces.

39. An interoperability instruction set as in claim 38, wherein the addressing field or fields of the instruction can further reference:

(5) one or more of the following additional address spaces in any combination;

(i) one or more disjoint virtual pointer address spaces;

(ii) a separate application heap element address space;

(iii) a virtualized local address space to the current function data space which is a contiguous subset of another address space; and

(iv) one or more virtualized object instance address spaces which are contiguous subsets of other address spaces.

40. An interoperability instruction set as in claim 38, wherein all address spaces are addressed by an N bit number, and a number of bits, M, of the N bits specify which of different possible 2 to the M power of address spaces the N-M remaining bits is actually referencing.

41. An interoperability instruction set as in claim 39, wherein all address spaces are addressed by an N bit number, and a number of bits, M, of the N bits specify which of different possible 2 to the M power of address spaces the N-M remaining bits is actually referencing.

42. An interoperability instruction set as in claim 40, where the address space is actually in units of 2 to the power of M of the native processor'"'"'s smallest directly accessible words so that using the N-M address space can still specify the entire direct address space of the native processor, only without the ability to directly address units of memory smaller then 2 to the power of M.

43. An interoperability instruction set as in claim 38, wherein virtual address pointer address spaces are used.

44. An interoperability instruction set as in claim 38, where the decoding of the address fields of instructions for data or code in any or all of the address spaces is checked by the processor decoding the instructions to ensure that no access will take place outside of the currently restricted bounds of the underlying memory, or other hardware accessible through the use of the decoded address fields.

52. A method for effecting an interoperability instruction set (IIS) in an apparatus, the method comprising:

providing a processor and memory coupled to the processor, and an input/output (I/O) interface to support communications with the processor by an entity external to the apparatus;

supporting execution interoperability methodologies involving at least one of a recruitment procedure, a renditioning procedure, a creationism procedure, a vertical layering procedure, a linear-tasking procedure, a social synchronization procedure, and a social security procedure; and

providing communications interoperability instructions for opening and maintaining a communication session and the procedures, data, content and/or other information that may be exchanged between communicating devices during a communication session.

53. A method as in claim 52, wherein:

the execution interoperability methodology comprises at least one interoperability instruction for carrying-out the interoperability methodology.

54. A computer program product for use in conjunction with a computer system or information appliance, the computer program product comprising a computer readable storage medium and a computer program mechanism embedded therein, the computer program mechanism comprising:

a program module that directs the computer system or information appliance having a processor and memory coupled to the processor and an input/output (I/O) interface to support communications with the processor by an entity external to the apparatus, to function in a specified manner for effecting an interoperability instruction set (IIS) in an apparatus, the program module including instructions for;

supporting execution interoperability methodologies involving at least one of a recruitment procedure, a renditioning procedure, a creationism procedure, a vertical layering procedure, a linear-tasking procedure, a social synchronization procedure, and a social security procedure; and

providing communications interoperability instructions for opening and maintaining a communication session and the procedures, data, content and/or other information that may be exchanged between communicating devices during a communication session.