Synchronous flash memory with status burst output

• US 20050289313A1
• Filed: 08/31/2005
• Published: 12/29/2005
• Est. Priority Date: 07/28/2000
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie F.
• Granted Patent: US 7,603,534 B2
• Time in Patent Office: Days
• US Class Current: 711/167
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/103 using serially addressed read-write data registers G11C7/1036 takes precedence
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. The memory can output data from storage registers on the data communication connections during a series of clock cycles to provide a burst of register data. The memory can also provide the register data in accordance to a defined clock latency value. The register data can include status data, operating setting data, manufacture identification, and memory device identification.

Claims

1. A method of operating to a synchronous memory device comprising:

executing a write operation on an array of the memory device;

providing a register read command from a processor to the memory device during the execution of the write operation;

receiving the register read command on an input of the memory device on a first clock cycle;

reading register data stored in a memory register; and

outputting the register data during a plurality of clock cycles on data communication connections of the synchronous memory device, wherein outputting the register data is delayed for a predefined clock latency period after receiving the register read command.

2. The method of claim 1 wherein the register data indicates a write status of the memory device.

3. The method of claim 1 further comprises:

setting a burst length of the synchronous memory device to define the plurality of clock cycles that the register data is output; and

setting a clock latency period.

4. The method of claim 1 wherein the synchronous memory device is a synchronous flash memory device having non-volatile memory cells.

5. The method of claim 1 wherein the register data is output y-clock cycles after receiving the read register command.

6. The method of claim 1 wherein the register data comprises operating data, status data, manufacture identification, or memory device identification.

7. The method of claim 1 wherein the predefined clock latency period is selected from either 2, 4, 8 or 16 clock cycles.

8. A method for operating to a synchronous memory device, the method comprising:

performing a write operation to an array of the memory device;

providing a status register read command for register data to an input of the memory device on a first clock cycle during the execution of the write operation; and

receiving the status register data during a plurality of clock cycles on data communication connections of the synchronous memory device, wherein receiving the register data is delayed for a predefined clock latency period after providing the status register read command.

9. The method of claim 8 wherein the plurality of clock cycles comprises four words and the plurality of clock cycles is substantially three cycles.

10. The method of claim 8 and further including receiving the plurality of clock cycles and the predefined clock latency period.

11. The method of claim 8 wherein performing the write operation, providing the register read command, and receiving the register data are accomplished by a processor coupled to the memory device.

12. The method of claim 8 and further including receiving operating data, status date, manufacturer identification, and memory device identification.

13. The method of claim 8 wherein a write operation can be performed on one bank of the array while reading data from remaining memory array banks.

14. The method of claim 13 wherein the synchronous memory device can perform a bank specific read operation while concurrently performing a write operation on another bank.

15. A method for operating a synchronous memory device in a system having a processor, the method comprising:

setting a burst length of the synchronous memory device to define the plurality of clock cycles that register data is output;

setting a clock latency period;

performing a write operation on the memory device;

performing a register read command for register data on the memory device during the execution of the write operation; and

receiving the burst of register data, on data communication connections of the synchronous memory device, during the burst length wherein receiving the burst of register data is delayed for a time equal to the clock latency period after providing the register read command.

16. The method of claim 15 wherein the clock latency period is selected from either 2, 4, 8 or 16 clock cycles.

17. The method of claim 15 wherein the register data comprises one of operating data, status data, manufacture identification, or memory device identification.

18. The method of claim 15 wherein the processor communicates with the memory device over a bi-directional data communication bus.

19. The method of claim 15 wherein the plurality of clock cycles comprises four words and the plurality of clock cycles is substantially three cycles.

20. The method of claim 15 wherein the synchronous memory device is a flash memory device comprising a memory array having non-volatile memory cells.