Simultaneous external read operation during internal programming in a flash memory device

• US 20050289314A1
• Filed: 06/23/2004
• Published: 12/29/2005
• Est. Priority Date: 06/23/2004
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Adusumilli, Vijaya P., Tehrani, Abbas S., Telecco, Nicola
• Granted Patent: US 7,159,069 B2
• Time in Patent Office: Days
• US Class Current: 711/168
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0859 with reload from main memory
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

A system and method for performing a simultaneous external read operation during internal programming of a memory device is described. The memory device is configured to store data randomly and includes a source location, a destination location, a data register, and a cache register. The data register is configured to simultaneously write data to the destination and to the cache register. The system further includes a processing device (e.g., a microprocessor or microcontroller) for verifying an accuracy of any data received through electrical communication with the memory device. The processing device is additionally configured to provide for error correction if the received data is inaccurate, add random data to the data, if required, and then transfer the error-corrected and/or random data modified data back to the destination location.

Claims

1. A system for performing a simultaneous external read operation during internal programming in a memory device, comprising:

a storage means for storing data randomly, said storage means including a source memory location, a destination memory location, a data register, and a cache register, said data register configured to simultaneously write data to said destination memory location and to said cache register, said source memory location and said destination memory location operable to communicate electronically with said data register, said data register additionally operable to communicate electronically with said cache register; and

a verification means for verifying accuracy of any data received through electrical communication with said storage means, said verification means additionally configured to provide for error correction of said data if said data is inaccurate.

2. The system of claim 1 wherein said storage means is a flash memory device.

3. The system of claim 2 wherein said flash memory device is a NAND-type device.

4. The system of claim 1 wherein said verification means is a microcontroller.

5. The system of claim 1 wherein said verification means is a microprocessor.

6. The system of claim 1 wherein electrical communications between said storage means and said verification means occurs over a serial bus.

7. The system of claim 1 wherein accuracy of said data is achieved by comparing said data with data originally stored in said source memory location.

8. The system of claim 1 wherein accuracy of said data is achieved through an error correction coding technique.

9. The system of claim 1 wherein said verification means is additionally configured to insert random data into said received data.

10. A method for performing a simultaneous external read operation during internal programming in a memory device, comprising:

copying original data stored at a source address location in said memory device to a data register; and

mirroring said original data copied to said data register while simultaneously copying said original data from said data register to a cache register and to a destination location.

11. The method of claim 10 further comprising:

transferring original data stored at said cache register to a processing device;

verifying integrity of said original data by comparing transferred original data with expected data stored at said source address location to locate potential errors in said transferred original data; and

performing error correction on said transferred original data if any errors are detected, thereby forming error-corrected data.

12. The method of claim 11 further comprising:

transferring error-corrected data from said processing device to said cache register;

mirroring a copy of said error-corrected data from said cache register to said data register; and

copying said error-corrected data from said data register to said destination location.

13. The method of claim 11 further comprising:

adding random data to said error-corrected data prior to form modified error-corrected data;

transferring modified error-corrected data from said processing device to said cache register;

mirroring a copy of said modified error-corrected data from said cache register to said data register; and

copying said modified error-corrected data from said data register to said destination location.

14. The method of claim 11 further comprising:

adding random data to said original data to form modified data;

transferring said modified data from said processing device to said cache register;

mirroring a copy of said modified data from said cache register to said data register; and

copying said modified data from said data register to said destination location.

15. The method of claim 11 wherein the processing device is a microcontroller.

16. The method of claim 11 wherein the processing device is a microprocessor.

17. A system for performing a simultaneous external read operation during internal programming in a memory device, comprising:

a memory device for storing data randomly, said memory device including a source memory location, a destination memory location, a data register, and a cache register, said data register configured to simultaneously write data to said destination memory location and to said cache register, said source memory location and said destination memory location operable to communicate electronically with said data register, said data register additionally operable to communicate with said cache register; and

a processing device for verifying accuracy of any data received through electrical communication with said memory device, said processing device additionally configured to provide for error correction of said data if said data is inaccurate.

18. The system of claim 17 wherein said memory device is a flash memory device.

19. The system of claim 18 wherein said flash memory device is a NAND-type device.

20. The system of claim 17 wherein said processing device is a microcontroller.

21. The system of claim 17 wherein said processing device is a microprocessor.

22. The system of claim 17 wherein electrical communications between said memory device and said processing device occurs over a serial bus.

23. The system of claim 17 wherein accuracy of said data is achieved by comparing said data with data originally stored in said source memory location.

24. The system of claim 17 wherein accuracy of said data is achieved through an error correction coding technique.

25. The system of claim 17 wherein said processing device is additionally configured to insert random data into said received data.