Semiconductor device, microcomputer, and electronic equipment

• US 20050289320A1
• Filed: 06/21/2005
• Published: 12/29/2005
• Est. Priority Date: 06/25/2004
• Status: Active Grant

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Kubota, Satoshi
• Granted Patent: US 7,363,465 B2
• Time in Patent Office: Days
• US Class Current: 711/202
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A semiconductor device comprising a bus master and a bus slave connected by a second bus is provided. A bus control unit (BCU) comprises a first relative address control circuit that performs a process for requesting the access using a relative address to a semiconductor storage medium through the second bus, the process including generation of a relative address corresponding to an absolute address based on the received absolute address and generation of an identification signal indicating the relative address. The memory controller comprises a second relative address control circuit that decides whether the received access address is a relative address or not and, if the received access address is a relative address, calculates an absolute address corresponding to the relative address.

Claims

1. A semiconductor device, comprising:

a bus master comprising a bus control circuit that receives an access address from a given module through a first bus and requests access based on the received access address to a memory through a second bus; and

a bus slave comprising a memory controller that controls access to the memory based on an access request received through the second bus;

wherein;

the bus control circuit of the bus master comprises a first relative address control circuit that performs a process for requesting the access using a relative address to the memory through the second bus, the process including generation of the relative address corresponding to an absolute address received through the first bus and generation of an identification signal indicating the relative address; and

the memory controller of the bus slave comprises a second relative address control circuit that decides whether the received access address is a relative address or not and, if the received access address is a relative address, calculates an absolute address corresponding to the relative address.

2. The semiconductor device according to claim 1, wherein an address bus of the second bus is a serial bus.

3. The semiconductor device according to claim 1, wherein data read or written through a data bus of the second bus is transferred based on a previous access data or a relative value from specified value data.

6. A microcomputer, comprising the semiconductor device according to claim 1.

7. Electronic equipment, comprising:

the microcomputer according to claim 6;

receiving input information; and

outputting a result processed by the microcomputer based on the input information.

4. A semiconductor device, comprising a bus master comprising a bus control circuit that receives an access address from a given module through a first bus and requests access based on the received access address to a memory through a second bus;

wherein;

the bus control circuit comprises a first relative address control circuit that performs a process for requesting the access using a relative address to the memory through the second bus, the process including generation of the relative address corresponding to an absolute address received through the first bus and generation of an identification signal indicating the relative address.

5. A semiconductor device, comprising a bus slave comprising a memory controller that controls access to the memory based on an access request received through the second bus;

wherein;

the memory controller comprises a second relative address control circuit that decides whether the received access address is a relative address or not and, if the received access address is a relative address, calculates an absolute address corresponding to the relative address.