Power fault handling method, apparatus, and system

• US 20050289393A1
• Filed: 06/29/2004
• Published: 12/29/2005
• Est. Priority Date: 06/29/2004
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Fullerton, Mark N., Bibikar, Vasudev J.
• Granted Patent: US 7,334,158 B2
• Time in Patent Office: Days
• US Class Current: 714/14
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 11/0721 within a central processing unit [CPU]
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers

Abstract

A processor may receive multiple signals corresponding to potential power faults. A control register in the processor may specify actions to be taken for each of the potential power faults.

Claims

1. A method comprising:

receiving one of a plurality of power fault indications;

accessing a control register programmed to specify a behavior based on an identity of the power fault indication; and

performing the behavior based on contents of the control register and the identity of the power fault indication.

2. The method of claim 1 wherein performing the behavior comprises entering a reduced power mode without allowing software intervention.

3. The method of claim 1 wherein performing the behavior comprises alerting a processor core of the power fault indication and allowing software intervention.

4. The method of claim 1 wherein the control register includes one control bit for each of the plurality of power fault indications.

5. The method of claim 1 wherein the control register includes more than one control bit for each of the plurality of power fault indications.

6. The method of claim 1 wherein receiving one of a plurality of power fault indications comprises receiving a main power supply fault indication or a backup power supply fault indication.

7. The method of claim 6 wherein the control register includes one bit corresponding to the main power supply fault indication and one bit corresponding to the backup power supply fault indication.

8. The method of claim 7 wherein performing the behavior comprises either allowing software control or not allowing software control of a transfer to a reduced power state.

9. A method comprising:

waking up from a reduced power state;

examining a register that includes information relating to a plurality of potential power faults;

if the reduced power state was entered as a result of a power fault, examining one or more control bits in the register that correspond to the power fault; and

based on a state of the one or more control bits, conditionally retrieving saved state information.

10. The method of claim 9 wherein examining a register comprises examining a register that includes a plurality of status bits, wherein each of the plurality of status bits corresponds to one of the plurality of potential power faults.

11. The method of claim 10 wherein examining one or more control bits comprises determining whether or not state information was saved when entering the reduced power state as a result of the power fault.

12. An article comprising:

a machine-readable medium having instructions stored thereon that when accessed result in a machine performing;

examining a register that includes information relating to a plurality of potential power faults;

if a reduced power state was entered as a result of a power fault, examining one or more control bits in the register that correspond to the power fault; and

based on a state of the one or more control bits, conditionally retrieving saved state information.

13. The article of claim 12 wherein examining a register comprises examining a register that includes a plurality of status bits, wherein each of the plurality of status bits corresponds to one of the plurality of potential power faults.

14. The article of claim 13 wherein examining one or more control bits comprises determining whether or not state information was saved when entering the reduced power state as a result of the power fault.

15. A processor comprising:

a register to hold a control bit for each of a plurality of potential power faults; and

a state machine coupled to receive power fault signals corresponding to the plurality of potential power faults, and to perform an operation when a power fault is received, wherein the operation is specified in part by the control bit for the received power fault.

16. The processor of claim 15 wherein based on a state of the control bit, the state machine conditionally causes the processor to enter a reduced power state without allowing software intervention.

17. The processor of claim 15 wherein based on a state of the control bit, the state machine conditionally allows software intervention.

18. The processor of claim 15 wherein the register includes multiple control bits for each of the plurality of potential power faults.

19. The processor of claim 15 wherein the register includes one control bit for each of two potential power faults.

20. The processor of claim 19 wherein the register further includes one status bit for each of the two potential power faults.

21. An electronic system comprising:

an antenna;

an analog circuit coupled to the antenna; and

a processor coupled to the analog circuit, the processor comprising a register to hold a control bit for each of a plurality of potential power faults, and a state machine coupled to receive power fault signals corresponding to the plurality of potential power faults and to perform an operation when a power fault is received, wherein the operation is specified in part by the control bit for the received power fault.

22. The electronic system of claim 21 wherein based on a state of the control bit, the state machine conditionally causes the processor to enter a reduced power state without allowing software intervention.

23. The electronic system of claim 21 wherein based on a state of the control bit, the state machine conditionally allows software intervention.