Intelligent probe chips/heads

• US 20050289415A1
• Filed: 06/24/2005
• Published: 12/29/2005
• Est. Priority Date: 06/24/2004
• Status: Abandoned Application

• Current Assignee: Lam Research Capital LLC
• Original Assignee: Celerity Research, Inc.
• Inventors: Dean, Vada W., DiOrio, Mark L.
• Application Number:
  US11/165,679
• Publication Number:
  US 20050289415A1
• Time in Patent Office: Days
• US Class Current: 714/724
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

An intelligent probe chip or probe head can include design-for-test (DFT) circuitry that would otherwise be required in a device being tested and/or implement testing functions so that less-expensive automated test equipment (ATE) can test the device.

Claims

1. A test system comprising a probe chip that includes:

a substrate;

active test circuitry integrated in and on the substrate; and

probe tips on the substrate and connected to the active test circuitry.

2. The system of claim 1, wherein the active test circuitry comprises circuitry that is selected from a group consisting of circuitry that supplies power to a device being tested, a timing or pattern signal generator for testing of the device, a data source, pin electronics, a controller, and DFT circuitry.

3. The system of claim 1, wherein the probe tips have a pattern that matches a pattern of electrical contacts on a device being tested.

4. The system of claim 3, wherein the probe tips are sufficiently rigid that a pressure used when the probe tips contact the electrical contacts for testing deform and planarize tops of the electrical contacts.

5. The system of claim 1, further comprising automated test equipment that is electrically connected to the probe chip.

6. The system of claim 1, wherein the chip further comprises a passive circuitry that implements a space transformation from electrical connections of a probe interface board to electrical connections of a device being tested.

7. A probe head comprising:

a substrate;

probe tips attached to the substrate; and

pin electronics electrically connected to the probe tips through the substrate.

8. The probe head of claim 7, wherein the substrate comprises a printed circuit board.

9. The probe head of claim 7, further comprising a control circuit mounted on the substrate.