High level synthesis method for semiconductor integrated circuit

• US 20050289499A1
• Filed: 06/23/2005
• Published: 12/29/2005
• Est. Priority Date: 06/25/2004
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Ogawa, Osamu, Hattori, Dai, Kurokawa, Keiichi, Toyonaga, Masahiko
• Granted Patent: US 7,237,220 B2
• Time in Patent Office: Days
• US Class Current: 716/104
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

A CDFG which is a graph representing calculations and a data flow included in the design specifications of a circuit is generated S101, a clock cycle required for the processing is obtained and thus an allocated resource connection graph is generated S102. When the allocated resource connection graph includes nodes to which hardware resources having the same function are allocated, a sharing edge for controlling sharing of the nodes is added between the nodes S103. A provisional layout of the allocated resource connection graph having the sharing edge added thereto is provided S104, and the nodes of the allocated resource connection graph are shared based on the layout result S105. The sharing edge is provided with attribute or weight such as attraction or repulsion. Thus, the distance between the nodes in the layout result is controlled and the degree at which the resources are shared is controlled.

Claims

1. A high level synthesis method for a semiconductor integrated circuit in consideration of layout, the high level synthesis method comprising:

a flow graph generation step of generating a flow graph associating calculations included in a function description of a design target circuit with nodes, and also associating a data flow included in the function description with edges;

an initial allocation scheduling step of allocating a usable hardware resource to each of the nodes of the flow graph;

allocating each node of the flow graph to a state corresponding to a clock cycle in consideration of the ordering represented by the edges of the flow graph;

obtaining a total number of states required for executing processing represented by the flow graph from a result of the state allocation; and

generating an allocated resource connection graph which has nodes corresponding to the nodes of the flow graph after the allocation of the hardware resource, and signal edges corresponding to the edges of the flow graph;

a sharing edge generation step of adding a sharing edge between a pair of nodes which are included in the allocated resource connection graph and to which sharable hardware resources are allocated, the sharing edge being added for controlling sharing of the nodes;

a resource arrangement step of providing a provisional layout of the allocated resource connection graph having the sharing edges added thereto; and

a resource sharing step of sharing nodes of the allocated resource connection graph based on a layout result obtained in the resource arrangement step.

2. A high level synthesis method according to claim 1, wherein:

when there are nodes allocated to different states in the state allocation result, the sharing edge generation step adds attraction force sharing edges for promoting sharing between the corresponding nodes of the allocated resource connection graph; and

when there are nodes allocated to the same state in the state allocation result, the sharing edge generation step adds repulsion force sharing edges for suppressing sharing between the corresponding nodes of the allocated resource connection graph; and

the resource arrangement step arranges the nodes connected by an attraction force sharing edge close to each other, and arranges the nodes connected by a repulsion force sharing edge discretely.

3. A high level synthesis method according to claim 2, wherein:

the sharing edge generation step gives a weight to an edge in the allocated resource connection graph; and

the resource arrangement step obtains the layout result based on the weight given by the sharing edge generation step.

4. A high level synthesis method according to claim 3, wherein when each node of the flow graph is re-allocated to a state in the range that a total state number does not exceed a value obtained in the initial allocation scheduling step, the sharing edge generation step sets the weight given to an attraction force sharing edge added between nodes, having a higher possibility of being allocated to different states, to a value which more highly promotes sharing.

5. A high level synthesis method according to claim 3, wherein when each node of the flow graph is re-allocated to a state in the range that a total state number does not exceed a value obtained in the initial allocation scheduling step, the sharing edge generation step sets the weight given to a repulsion force sharing edge added between nodes, having a lower possibility of being allocated to different states, to a value which more highly suppresses sharing.

6. A high level synthesis method according to claim 3, wherein when the nodes allocated to the same state in the state allocation result are connected via one or more signal edges in the same state, the sharing edge generation step sets the weight given to the repulsion force sharing edge, added between the corresponding nodes of the allocated resource connection graph, to an invalid value.

7. A high level synthesis method according to claim 1, wherein when there are nodes allocated to different states in the state allocation result, the sharing edge generation step adds attraction force sharing edges for promoting sharing between the corresponding nodes of the allocated resource connection graph;

and

the resource arrangement step arranges the nodes connected by the attraction force sharing edge close to each other based on the weight given in the sharing edge generation step.

8. A high level synthesis method according to claim 1, wherein the resource arrangement step is a scheduling and resource arrangement step of re-allocating each node of the flow graph to each state in the range that a total state number does not exceed a value obtained in the initial allocation scheduling step, and of providing a provisional layout of the allocated resource connection graph having the sharing edges added thereto.

9. A high level synthesis method according to claim 8, further comprising a sharing edge re-generation step of re-adding a sharing edge to the allocated resource connection graph processed in the resource sharing step;

wherein the scheduling and resource arrangement step, the resource sharing step, and the sharing edge re-generation step are repeated until a predetermined condition is fulfilled.

10. A high level synthesis method according to claim 1, wherein the resource sharing step comprises:

a sharing target selection step of selecting a set of nodes to be shared from the allocated resource connection graph;

a selected resource sharing step of sharing the nodes selected in the sharing target selection step;

a sharing edge re-generation step of re-adding a sharing edge to the allocated resource connection graph processed in the selected resource sharing step; and

a layout result correction step of correcting the layout result obtained in the resource arrangement step based on the allocated resource connection graph processed in the sharing edge re-generation step;

wherein the resource sharing step is an incremental improving resource sharing step of repeating the sharing target selection step, the selected resource sharing step, the sharing edge re-generation step and the layout result correction step until a predetermined condition is fulfilled.

11. A high level synthesis method according to claim 1, wherein the resource sharing step obtains a priority level of a pair of nodes which are included in the allocated resource connection graph and to which sharable hardware resources are allocated, and shares the nodes in a predetermined range, starting from the pair of nodes having a higher priority level.

12. A high level synthesis method according to claim 11, wherein the priority level in the resource sharing step is in inverse proportion to a distance between the nodes in the layout result obtained in the resource arrangement step.

13. A high level synthesis method according to claim 11, wherein:

the sharing edge generation step gives a weight to an edge in the allocated resource connection graph; and

the priority level in the resource sharing step is in proportion to a value obtained by dividing the weight given to an edge added between the nodes by the distance between the nodes in the layout result obtained in the resource arrangement step.

14. A high level synthesis method according to claim 11, wherein:

the sharing edge generation step gives a weight to an edge in the allocated resource connection graph; and

the priority level in the resource sharing step is calculated using a calculation formula including a term in proportion to the weight given to the edge added between the nodes and a term in inverse proportion to the distance between the nodes in the layout result obtained in the resource arrangement step.

15. A high level synthesis method according to claim 3, further comprising:

a layout difficulty level evaluation step of evaluating a layout difficulty level of the allocated resource connection graph having sharing edges added thereto;

an attraction force sharing edge selection step of, when the layout difficulty level evaluation step determines that the layout is difficult, selecting an attraction force sharing edge having a low sharing efficiency from the allocated resource connection graph having sharing edges added thereto; and

an attraction force sharing edge weight reduction step of reducing the weight of the attraction force sharing edge selected in the attraction force sharing edge selection step.

16. A high level synthesis method according to claim 7, further comprising:

a layout difficulty level evaluation step of evaluating a layout difficulty level of the allocated resource connection graph having sharing edges added thereto;

an attraction force sharing edge selection step of, when the layout difficulty level evaluation step determines that the layout is difficult, selecting an attraction force sharing edge having a low sharing efficiency from the allocated resource connection graph having sharing edges added thereto; and

an attraction force sharing edge deleting step of deleting the attraction force sharing edge selected in the attraction force sharing edge selection step.

17. A high level synthesis method according to claim 15, wherein the layout difficulty level evaluation step evaluates the layout difficulty level based on a sum of weights given to signal edges and attraction force sharing edges in the allocated resource connection graph having the sharing edges added thereto.

18. A high level synthesis is method according to claim 15, wherein the layout difficulty level evaluation step evaluates the layout difficulty level based on a difference between a sum of weights given to signal edges and a sum of weights given to attraction force sharing edges in the allocated resource connection graph having the sharing edges added thereto.

19. A high level synthesis method according to claim 15, wherein the layout difficulty level evaluation step evaluates the layout difficulty level based on a ratio of a sum of weights given to attraction force sharing edges with respect to a sum of weights given to the signal edges and the attraction force sharing edges in the allocated resource connection graph having the sharing edges added thereto.

20. A high level synthesis method according to claim 15, wherein the layout difficulty level evaluation step adds a node, to which a dummy hardware resource is allocated, to an attraction force sharing edge having a weight of a predetermined value or less based on the allocated resource connection graph having the sharing edges added thereto, thereby generating an allocated resource connection graph for evaluation;

obtains a total number of primary adjacent nodes connected to each of all the nodes in the allocated resource connection graph for evaluation via one signal edge and obtains a total number of up-to-secondary adjacent nodes connected to each of all the nodes in the allocated resource connection graph for evaluation via two or less signal edges; and

evaluates the layout difficulty level based on the difference between the logarithms of the two total numbers.

21. A high level synthesis method according to claim 15, wherein, when hardware resources allocated to nodes connected to both ends of a certain attraction force sharing edge have a large difference in bit length, the attraction force sharing edge selection step selects the certain attraction force sharing edge as an attraction force sharing edge having a low sharing efficiency.

22. A high level synthesis method according to claim 15, wherein, when hardware resources allocated to nodes connected to both ends of a certain attraction force sharing edge have a large difference in delay time, the attraction force sharing edge selection step selects the certain attraction force sharing edge as an attraction force sharing edge having a low sharing efficiency.

23. A high level synthesis method according to claim 15, wherein, when one of hardware resources allocated to nodes connected to both ends of a certain attraction force sharing edge has a smaller area than the other hardware resource, and the value of the smaller area is sufficiently small, the attraction force sharing edge selection step selects the certain attraction force sharing edge as an attraction force sharing edge having a low sharing efficiency.

24. A high level synthesis method according to claim 15, wherein the attraction force sharing edge selection step selects an attraction force sharing edge given a weight which suppresses sharing as an attraction force sharing edge having a low sharing efficiency.

25. A high level synthesis method according to claim 15, wherein when lifetimes of output values of hardware resources allocated to nodes connected to both ends of a certain attraction force sharing edge have a high probability of overlapping, the attraction force sharing edge selection step selects the certain attraction force sharing edge as an attraction force sharing edge having a low sharing efficiency.

26. A high level synthesis method according to claim 15, wherein in the state where hardware resources allocated to nodes connected to both ends of a certain attraction force sharing edge are different in the bit length and are different in the delay time, one of the hardware resources has a smaller area than the other hardware resource, and the lifetimes of output values of these hardware resources have a certain probability of overlapping;

and in the state where an evaluation value is provided by a calculation equation which includes a term in proportion to the difference in the bit length, a term in proportion to the difference in the delay time, a term in inverse proportion to the value of the smaller area, a term in proportion to the probability of overlapping, and a term in inverse proportion to the weight given to the attraction force sharing edge;

the attraction force sharing edge selection step selects an attraction force sharing edge having a high evaluation value obtained by the calculation equation as an attraction force sharing edge having a low sharing efficiency.

27. A high level synthesis method according to claim 16, wherein the layout difficulty level evaluation step evaluates the layout difficulty level based on a sum of weights given to signal edges and attraction force sharing edges in the allocated resource connection graph having the sharing edges added thereto.

28. A high level synthesis method according to claim 16, wherein the layout difficulty level evaluation step evaluates the layout difficulty level based on a difference between a sum of weights given to signal edges and a sum of weights given to attraction force sharing edges in the allocated resource connection graph having the sharing edges added thereto.

29. A high level synthesis method according to claim 16, wherein the layout difficulty level evaluation step evaluates the layout difficulty level based on a ratio of a sum of weights given to attraction force sharing edges with respect to a sum of weights given to the signal edges and the attraction force sharing edges in the allocated resource connection graph having the sharing edges added thereto.

30. A high level synthesis method according to claim 16, wherein the layout difficulty level evaluation step adds a node, to which a dummy hardware resource is allocated, to an attraction force sharing edge having a weight of a predetermined value or less based on the allocated resource connection graph having the sharing edges added thereto, thereby generating an allocated resource connection graph for evaluation;

obtains a total number of primary adjacent nodes connected to each of all the nodes in the allocated resource connection graph for evaluation via one signal edge and obtains a total number of up-to-secondary adjacent nodes connected to each of all the nodes in the allocated resource connection graph for evaluation via two or less signal edges; and

evaluates the layout difficulty level based on the difference between the logarithms of the two total numbers.

31. A high level synthesis method according to claim 16, wherein, when hardware resources allocated to nodes connected to both ends of a certain attraction force sharing edge have a large difference in bit length, the attraction force sharing edge selection step selects the certain attraction force sharing edge as an attraction force sharing edge having a low sharing efficiency.

32. A high level synthesis method according to claim 16, wherein, when hardware resources allocated to nodes connected to both ends of a certain attraction force sharing edge have a large difference in delay time, the attraction force sharing edge selection step selects the certain attraction force sharing edge as an attraction force sharing edge having a low sharing efficiency.

33. A high level synthesis is method according to claim 16, wherein, when one of hardware resources allocated to nodes connected to both ends of a certain attraction force sharing edge has a smaller area than the other hardware resource, and the value of the smaller area is sufficiently small, the attraction force sharing edge selection step selects the certain attraction force sharing edge as an attraction force sharing edge having a low sharing efficiency.

34. A high level synthesis method according to claim 16, wherein the attraction force sharing edge selection step selects an attraction force sharing edge given a weight which suppresses sharing as an attraction force sharing edge having a low sharing efficiency.

35. A high level synthesis method according to claim 16, wherein when lifetimes of output values of hardware resources allocated to nodes connected to both ends of a certain attraction force sharing edge have a high probability of overlapping, the attraction force sharing edge selection step selects the certain attraction force sharing edge as an attraction force sharing edge having a low sharing efficiency.

36. A high level synthesis method according to claim 16, wherein in the state where hardware resources allocated to nodes connected to both ends of a certain attraction force sharing edge are different in the bit length and are different in the delay time, one of the hardware resources has a smaller area than the other hardware resource, and the lifetimes of output values of these hardware resources have a certain probability of overlapping;

and in the state where an evaluation value is provided by a calculation equation which includes a term in proportion to the difference in the bit length, a term in proportion to the difference in the delay time, a term in inverse proportion to the smaller area, a term in proportion to the probability of overlapping; and

a term in inverse proportion to the weight given to the attraction force sharing edge;

the attraction force sharing edge selection step selects an attraction force sharing edge having a higher evaluation value obtained by the calculation equation as an attraction force sharing edge having a low sharing efficiency.

37. A high level synthesis method according to claim 1, wherein the resource arrangement step provides a provisional layout of the allocated resource connection graph having sharing edges added thereto in accordance with a layout model which allows nodes, to which sharable hardware resources are allocated, to be arranged at the same position.

38. A high level synthesis method according to claim 37, wherein in the layout model in the resource arrangement step, the number of nodes which can be arranged at the same position is limited.

39. A high level synthesis method according to claim 37, wherein when a new node is arranged at the same position as another node already arranged, the resource arrangement step estimates a delay time of a selection circuit provided on an input side of the hardware resource provisionally shared by the nodes arranged at the same position;

and then estimates the processing time of the state to which the nodes are allocated, including the delay time of the selection circuit; and

when the estimated processing time is close to the clock cycle, the resource arrangement step moves the newly arranged node to another position and prohibits arranging a node at the same position as the node already arranged in the subsequent processing.

40. A high level synthesis method according to claim 37, wherein when providing the provisional layout of the allocated resource connection graph having the sharing edges added thereto, the resource arrangement step uses an evaluation function by which an evaluation value is decreased when the number of nodes arranged at the same position exceeds a predetermined value.

41. A high level synthesis method according to claim 1, wherein the resource arrangement step converts a node of the allocated resource connection graph having sharing edges added thereto into a plurality of unit elements and connection elements connecting the unit elements in accordance with the hardware resource allocated to the node, and provides a provisional layout of the post-conversion allocated resource connection graph.

42. A high level synthesis method according to claim 41, wherein when the hardware resource allocated to a node of the allocated resource connection graph having sharing edges added thereto is a hard resource having a fixed shape, the resource arrangement step provides the connection elements at high density;

and when the hardware resource allocated to a node of the allocated resource connection graph having sharing edges added thereto is a soft resource having a variable shape, the resource arrangement step provides the connection elements at low density.

43. A high level synthesis method according to claim 42, wherein the resource arrangement step provides a connection element having a large weight to a hardware resource as the hard resource;

provides a connection element having a small weight to a hardware resource as the soft resource; and

provides a provisional layout of the post-conversion allocated resource connection graph based on the weight given to each connection element.

44. A high level synthesis method according to claim 42, wherein the hardware resource as the hard resource is provided with connection elements for connecting all the unit elements which are adjacent to each other in up, down, right and left directions.

45. A high level synthesis method according to claim 42, wherein the hardware resource as the soft resource is provided with one connection element for connecting all the unit elements.

46. A high level synthesis method according to claim 42, wherein the hardware resource as the soft resource is provided with a connection element to be connected with one or more but three or less unit elements, among the unit elements which are adjacent to each other in up, down, right and left directions.

47. A high level synthesis method according to claim 42, wherein the hardware resource as the soft resource is provided with a connection element for connecting a central unit element and each of the other unit elements.

48. A high level synthesis method according to claim 42, wherein the hardware resource as the soft resource is provided with a connection element in a style in accordance with an architecture of the hardware resource.

49. A high level synthesis method according to claim 1, wherein the flow graph generation step generates a control/data flow graph including a data flow graph representing calculations and a data flow included in the functional description and a control flow graph representing execution control of the calculations included in the functional description.