Electronic lock

• US 20060000247A1
• Filed: 07/22/2005
• Published: 01/05/2006
• Est. Priority Date: 12/08/1999
• Status: Abandoned Application

• Current Assignee: Charles W. Moon, Ernst K. Mitchell, John J. Kimes, Mohamad A. Khalil
• Original Assignee: Charles W. Moon, Ernst K. Mitchell, John J. Kimes, Mohamad A. Khalil
• Inventors: Khalil, Mohamad A., Moon, Charles W., Mitchell, Ernst K., Kimes, John J.
• Application Number:
  US11/187,561
• Publication Number:
  US 20060000247A1
• Time in Patent Office: Days
• US Class Current: 70/283
• CPC Class Codes: E05B 13/004 by locking the spindle, follower, or the like
• CPC Class Codes: E05B 2047/0024 Cams
• CPC Class Codes: E05B 2047/003 of the overload- slip- or friction type
• CPC Class Codes: E05B 47/0012 with rotary electromotors actuators with rotary electromotors per se H02K7/06, H02K23/68
• CPC Class Codes: E05B 47/0673 with a rectilinearly moveable blocking element
• CPC Class Codes: G07C 2009/00373 whereby the wake-up circuit is situated in the lock
• CPC Class Codes: G07C 2209/08 With time considerations, e.g. temporary activation, valid time window or time limitations
• CPC Class Codes: G07C 9/00309 operated with bidirectional data transmission between data carrier and locks
• CPC Class Codes: G07C 9/00658 operated by passive electrical keys
• CPC Class Codes: G07C 9/00722 with magnetic components, e.g. magnets, magnetic strips, metallic inserts mechanical locks operated by permanent magnets E05B47/0038
• CPC Class Codes: Y10T 70/5226 Combined dead bolt and latching bolt
• CPC Class Codes: Y10T 70/7068 Actuated after correct combination recognized [e.g., numerical, alphabetical, or magnet[s] pattern]
• CPC Class Codes: Y10T 70/7073 Including use of a key
• CPC Class Codes: Y10T 70/7102 And details of blocking system [e.g., linkage, latch, pawl, spring]
• CPC Class Codes: Y10T 70/713 Dogging manual operator
• CPC Class Codes: Y10T 70/7136 Key initiated actuation of device

Abstract

A lockset controller that functions in either a low power sleep mode or an active mode and includes a processor that'"'"'s inactive in the sleep mode and active in the active mode. A wakeup control module switches the controller from the sleep mode to the active mode when a wakeup event occurs. A key card control module acts as an interface between a key card reader and the controller such that electronic data may be transferred between the two devices. A motor driver module drives an electrical motor that moves a locking mechanism component of the lockset apparatus between locked and unlocked states. The controller switches from sleep to active mode when the processor receives a wakeup signal. Once in active mode, if the processor receives an authorized data signal, the processor transmits a power signal that causes the electrical motor to unlock the locking mechanism.

Claims

1. An electronic lockset controller (28) for use with a door-mounted lockset apparatus (10) and operable to function in a low power sleep mode and an active mode, the lockset controller comprises:

a core processor (340) capable of controlling the operation of electronic devices within the lockset controller according to a set of electronic instructions and including a wakeup signal input, a key card signal input, and a motor signal output, the processor being inactive when the lockset controller is in the sleep mode and active when the lockset controller is in the active mode,

a wakeup control module (312) capable of switching the lockset controller from the sleep mode to the active mode upon the happening of a wakeup event and including an external wakeup signal input for receiving an electronic signal indicating the occurrence of a wakeup event that is external to the lockset controller, an internal wakeup signal input for receiving an electronic signal indicating the occurrence of a wakeup event that is internal to the lockset controller, and a wakeup signal output connected to the wakeup signal input of the processor for transmitting an electronic wakeup signal indicating that a wakeup event has occurred,

a key card control module (314) capable of acting as an interface between a key card reader (26) and the lockset controller such that electronic data may be transferred between the two devices, the key card control including a key card signal input connected to the key card reader for receiving an electronic signal representative of information stored on a key card, and a key card signal output coupled to the key card signal input of the processor for transmitting an electronic data signal representative of the information stored on the key card, and

a motor driver module (326) capable of driving an electrical motor that moves a locking mechanism component of the lockset apparatus between locked and unlocked states, the motor driver comprising a motor signal input connected to the motor signal output of the processor for receiving an electronic power signal representative of the amount of power intended to drive the electrical motor and a motor signal output connected to the electrical motor for transmitting an electrical signal representative of the power signal, wherein the lockset controller switches from sleep mode to active mode when the processor receives a wakeup signal and, once in active mode, if the processor receives an authorized data signal the processor transits a power signal that causes the electrical motor to unlock the locking mechanism.

2. A lockset controller (28) as defined in claim 1 further including:

a low power oscillator module (302) capable of producing a first clock signal and having a clock output,

a real time clock module (304) capable of acting as a counter and having a clock input connected to the low power oscillator clock output and a signal output connected to the internal wakeup signal input of the wakeup control module (312), and

a high speed oscillator (306) capable of producing a second clock signal and having a clock output connected to the core processor (340), wherein the real time clock periodically transmits an internal wakeup signal based on the first clock signal to the wakeup control when the lockset controller is in sleep mode, the high speed oscillator drives the core processor with the second clock signal when the lockset controller is in active mode.

3. A lockset controller (28) as defined in claim 2 wherein the frequency with which the real time clock module (304) transmits the internal wakeup signal is programmable.

4. A lockset controller (28) as defined in claim 1 further including a switch control module (308) having a switch input connected to a switch external to the lockset controller and a switch output connected to the external wakeup signal input of the wakeup control module (312), wherein the switch control transmits an external wakeup signal based on the state of the external switch to the wakeup control.

5. A lockset controller (28) as defined in claim 4 wherein the switch control module (308) further includes a programmable signal verification for ensuring accuracy of the external wakeup signal.

6. A lockset controller (28) as defined in claim 4 wherein the switch control module (308) further includes power conserving power pullups.

7. A lockset controller (28) as defined in claim 1 wherein the key card reader (26) is capable of communicating with a smart key card having its own processor, RAM, and ROM, wherein the lockset controller supplies the smart key card with power and a clock signal.

8. A lockset controller (28) as defined in claim 7 wherein the key card control module (314) further includes a programmable power output capable of supplying smart key cards with power signals of various voltage levels.

9. A lockset controller (28) as defined in claim 7 wherein the key card control module (314) further includes a programmable clock output capable of supplying smart key cards with clock signals of various frequencies.

10. A lockset controller (28) as defined in claim 1 wherein the key card reader (26) includes a magnetic head reader that is capable of communicating with a key card having a magnetic strip.

11. A lockset controller (28) as defined in claim 1 further including a programmable power control module (322) capable of programmably adjusting the voltage level of signals used throughout.

12. A lockset controller (28) as defined in claim 1 further including a motor current sensing module (324) capable of determining the position of the locking mechanism component based on the amount of electrical current sent to the electrical motor.

13. A lockset controller (28) as defined in claim 1 wherein the motor driver module (326) drives the electrical motor for at least a minimum motor run time and no longer than a maximum motor run time.

14. A lockset controller (28) as defined in claim 1 wherein the motor driver module (326) that uses electrical current sinks and electrical current sources to drive the electrical motor.

15. A lockset controller (28) as defined in claim 1 further including an LED driver (328) that uses electrical current sinks and electrical current sources to illuminate an LED display module (140).

16. A lockset controller (28) as defined in claim 1 further including a battery level sensing module (330) capable of determining the battery power of the lockset controller.

17. A lockset controller (28) as defined in claim 15 wherein the battery level sensing module (330) is programmable.

18. A lockset controller (28) as defined in claim 1 further including an XRAM memory module (334) capable of storing electronic instructions for the core processor (340) wherein the core processor may receive electronic instructions from either the XRAM memory or a memory source external to the lockset controller.

19. A lockset controller (28) as defined in claim 17 further including a flash memory decode module (338) electronically connected to both the XRAM memory module (334) and the external memory source such that when the core processor (340) writes to the external memory source, the flash memory decode directs the core processor to receive instructions from the XRAM memory.

20. A lockset controller (28) as defined in claim 1 wherein the wakeup control module (312) will not send the wakeup signal to the core processor (340) if the core processor is already in active mode.