Dual-sided capacitor and method of formation

• US 20060001052A1
• Filed: 09/06/2005
• Published: 01/05/2006
• Est. Priority Date: 08/22/2002
• Status: Active Grant

• Current Assignee: Er-Xuan Ping, Shenlin Chen
• Original Assignee: Er-Xuan Ping, Shenlin Chen
• Inventors: Ping, Er-Xuan, Chen, Shenlin
• Granted Patent: US 7,355,232 B2
• Time in Patent Office: Days
• US Class Current: 257/213
• CPC Class Codes: H01L 28/84 being a rough surface, e.g. using hemispherical grains
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/312 with a bit line higher than the capacitor
• CPC Class Codes: H10B 12/318 the storage electrode having multiple segments
• CPC Class Codes: H10B 12/482 Bit lines

Abstract

A dual-sided HSG capacitor and a method of fabrication are disclosed. A thin native oxide layer is formed between a doped polycrystalline layer and a layer of hemispherical grained polysilicon (HSG) as part of a dual-sided lower capacitor electrode. Prior to the dielectric formation, the lower capacitor electrode may be optionally annealed to improve capacitance.

Claims

1-50. -50. (canceled)

51. A memory device comprising:

an array of memory cells, each memory cell of said array comprising a transistor and a capacitor, said capacitor comprising;

a dual-sided electrode comprising an oxide layer between two conductive layers;

a dielectric layer in contact with said dual-sided electrode; and

a conductive layer over said dielectric layer.

52. The memory device of claim 51, wherein one of said two conductive layers is a doped polycrystalline layer in contact with said oxide layer.

53. The memory device of claim 52, wherein the other one of said two conductive layers is a layer of hemispherical grained polysilicon, said oxide layer being located between said doped polycrystalline layer and said layer of hemispherical grained polysilicon.

54. The memory device of claim 51, wherein said oxide layer is a native oxide layer.

55. The memory device of claim 54, wherein said native oxide layer has a thickness of about 5 Angstroms to about 50 Angstroms.

56. The memory device of claim 52, wherein said doped polycrystalline layer is formed of a material selected from the group consisting of hemispherical grained polysilicon, silicon, germanium, or any alloy of silicon and germanium.

57. The memory device of claim 51, wherein said dual-sided electrode is a lower electrode of said capacitor.

58. The memory device of claim 51, wherein said dual-sided electrode is an PH₃ annealed dual-sided electrode.

59. The memory device of claim 51, wherein said oxide layer is an ALD oxide layer.

60. The memory device of claim 51, wherein said oxide layer is a thermally grown oxide layer.

61. A semiconductor device comprising:

an electrical circuit formed over a semiconductor substrate, said electrical circuit comprising a capacitor, said capacitor further comprising a dual-sided capacitor electrode comprising;

an annealed doped polycrystalline layer having HSG grains of a first thickness;

a layer of hemispherical grained polysilicon having HSG grains of a second thickness; and

an oxide layer between said annealed doped polycrystalline layer and said layer of hemispherical grained polysilicon.

62. The semiconductor device of claim 61 further comprising an oxide layer between said annealed doped polycrystalline layer and said layer of hemispherical grained polysilicon.

63. The semiconductor device of claim 62, wherein said oxide layer has a thickness of about 5 Angstroms to about 50 Angstroms.

64. The semiconductor device of claim 61, wherein said second thickness is greater than said first thickness.

65. The semiconductor device of claim 61, wherein said second thickness is of about 100 Angstroms to about 500 Angstroms.

66. The semiconductor device of claim 61, wherein said first thickness is of about 10 Angstroms to about 50 Angstroms.

67. The semiconductor device of claim 61, wherein said dual-sided electrode is a lower electrode of a capacitor.

68. A processor system comprising:

a processor; and

a memory coupled to said processor, at least one of said processor and said memory comprising a capacitor, said capacitor comprising;

a dual-sided electrode comprising an oxide layer between two conductive layers;

a dielectric layer in contact with said dual-sided electrode; and

a conductive layer over said dielectric layer.

69. The processor system of claim 68, wherein said oxide layer is a native oxide layer having a thickness of about 5 Angstroms to about 50 Angstroms.

70. The processor system of claim 68, wherein said native oxide layer is formed between said doped polycrystalline layer and said layer of hemispherical grained polysilicon.

71. The processor system of claim 68, wherein said doped polycrystalline layer is formed of a material selected from the group consisting of hemispherical grained polysilicon, silicon, germanium, or any alloy of silicon and germanium.

72. The processor system of claim 68, wherein said dual-sided electrode is a lower electrode.

73. The processor system of claim 68, wherein native oxide layer is an ALD oxide layer.

74. The processor system of claim 68, wherein said oxide layer is a thermally grown oxide layer.

75. An electronic system comprising:

at least one electrical circuit containing a capacitor, said capacitor comprising;

a dual-sided electrode comprising an oxide layer between two conductive layers;

a dielectric layer in contact with said dual-sided electrode; and

a conductive layer over said dielectric layer.

76. The electronic system of claim 75, wherein one of said two conductive layers is a doped polycrystalline layer in contact with said oxide layer.

77. The electronic system of claim 76, wherein the other one of said two conductive layers is a layer of hemispherical grained polysilicon, said oxide layer being located between said doped polycrystalline layer and said layer of hemispherical grained polysilicon.

78. The electronic system of claim 75, wherein said oxide layer is a native oxide layer.

79. The electronic system of claim 78, wherein said native oxide layer has a thickness of about 5 Angstroms to about 50 Angstroms.

80. The electronic system of claim 75, wherein said dual-sided electrode is a lower electrode of said capacitor.

81. The electronic system of claim 75, wherein said dual-sided electrode is an PH₃ annealed dual-sided electrode.

82. The electronic system of claim 75, wherein said oxide layer is an ALD oxide layer.

83. The electronic system of claim 75, wherein said oxide layer is a thermally grown oxide layer.