Semiconductor device and manufacturing method of the same

• US 20060001097A1
• Filed: 11/24/2004
• Published: 01/05/2006
• Est. Priority Date: 07/01/2004
• Status: Abandoned Application

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Suzuki, Teruo, Nomura, Toshio, Hashimoto, Kenji
• Application Number:
  US10/995,513
• Publication Number:
  US 20060001097A1
• Time in Patent Office: Days
• US Class Current: 257/355
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements

Abstract

A protection transistor which protects an internal transistor in an internal circuit from breakage due to static electricity occurring between power supply pads is provided. A conductivity type of a first p-well constructing a channel of the protection transistor corresponds to a conductivity type of a second p-well constructing a channel of the internal transistor. An impurity concentration of the first p-well is higher than an impurity concentration of the second p-well. Accordingly, drain junction of the protection transistor is sharper than drain junction of the internal transistor, and starting voltage of a parasitic bipolar operation of the protection transistor is lower than that of the internal transistor. Therefore, the internal circuit can be properly protected from an ESD surge.

Claims

1. A semiconductor device, comprising:

an internal transistor constructing an internal circuit; and

a protection transistor which protects said internal transistor from breakage due to static electricity occurring between power supply pads, a conductivity type of a channel of said protection transistor corresponding to a conductivity type of said internal transistor, and drain junction of said protection transistor being sharper than drain junction of said internal transistor.

2. The semiconductor device according to claim 1, wherein an impurity concentration of the channel of said protection transistor is higher than that of a channel of said internal transistor.

3. The semiconductor device according to claim 1, wherein said protection transistor has an impurity diffusion layer formed between the channel and a drain, having a higher impurity concentration than the channel, and having the same conductivity type as the channel.

4. The semiconductor device according to claim 1, wherein an impurity concentration of a drain of said protection transistor is higher than that of a drain of said internal transistor.

5. The semiconductor device according to claim 1, wherein said internal transistor and protection transistor are n-channel MOS transistors.

6. The semiconductor device according to claim 1, further comprising a second protection transistor which protects said internal transistor from breakage due to static electricity occurring to an input and output pad.

7. The semiconductor device according to claim 6, further comprising a resistance element connected between said second protection transistor and said internal circuit.

8. The semiconductor device according to claim 6, wherein said second protection transistor is an n-channel MOS transistor.

9. A manufacturing method of a semiconductor device, comprising the step of:

forming an internal transistor constructing an internal circuit, and a protection transistor which protects the internal transistor from breakage due to static electricity occurring between electric power pads, a conductivity type of a channel of the protection transistor being made to correspond to a conductivity type of the internal transistor, and drain junction of the protection transistor being made sharper than drain junction of the internal transistor.

10. The manufacturing method according to claim 9, wherein said step of forming the protection transistor comprises the step of forming a channel having a higher impurity concentration than that of a channel of the internal transistor.

11. The manufacturing method according to claim 9, wherein said step of forming the protection transistor comprises the steps of:

forming a channel;

forming a drain; and

forming an impurity diffusion layer, between the channel and the drain, having a higher impurity concentration than the channel and having the same conductivity type as the channel.

12. The manufacturing method according to claim 9, wherein said step of forming the protection transistor comprises the step of forming a drain having a higher impurity concentration than that of a drain of the internal transistor.

13. The manufacturing method according to claim 9, wherein n-channel MOS transistors are formed as the internal transistor and the protection transistor.

14. The manufacturing method according to claim 9, a second protection transistor which protects the internal transistor from breakage due to static electricity occurring to an input and output pad is formed in parallel with the internal transistor and the protection transistor.

15. The manufacturing method according to claim 14, wherein an n-channel MOS transistor is formed as the second protection transistor.

16. The manufacturing method according to claim 14, wherein said step of forming the second protection transistor comprises the steps of:

forming a channel having a lower impurity concentration than the channel of the protection transistor; and

forming a part of a drain in parallel with the drain of the protection transistor.

17. The manufacturing method according to claim 9, further comprising the step of forming a second internal transistor constructing the internal circuit and operating at a lower voltage than the internal transistor, in parallel with the internal transistor and the protection transistor.

18. The manufacturing method according to claim 17, wherein an impurity concentration of a channel of the second internal transistor is made equal to that of the channel of the protection transistor.

19. The manufacturing method according to claim 9, wherein said step of forming the protection transistor comprises the steps of:

forming a drain of an LDD structure;

forming a silicide block on the drain; and

forming a silicide layer on a surface of the drain.

20. The manufacturing method according to claim 9, wherein said step of forming the protection transistor comprises the steps of:

forming a low concentration diffusion layer;

forming a silicide block on the low concentration diffusion layer;

forming a high concentration diffusion layer superposed on part of the low concentration diffusion layer with the silicide block as a mask; and

forming a silicide layer on a surface of the high concentration diffusion layer.