Anti-cross conduction drive control circuit and method

• US 20060001459A1
• Filed: 01/12/2005
• Published: 01/05/2006
• Est. Priority Date: 07/01/2004
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Audy, Jonathan M.
• Granted Patent: US 7,187,226 B2
• Time in Patent Office: Days
• US Class Current: 327/112
• CPC Class Codes: H02M 1/38 Means for preventing simultaneous conduction of switches
• CPC Class Codes: H03K 17/08122 in field-effect transistor switches
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor

Abstract

An anti-cross conduction driver control circuit and method prevent the occurrence of race conditions and avoid cross-conduction between series-connected power devices, typically MOSFETs, controlled in accordance with the present invention. Individual state machines are connected across the inputs and outputs of each power device driver, and are arranged to accurately determine when the driver has completed a task requested of it. Each state machine produces a “lockout” signal based on driver status, which is used to inhibit the operation of the opposite driver under prescribed conditions, and to thereby prevent cross-conduction between the series-connected power devices.

Claims

1. An anti-cross conduction driver control circuit, comprising:

first and second normally complementary input signals, each of which has on and off states;

first and second lockout signals which have lockout and non-lockout states;

a first driver turn-on signal having on and off states, said first driver turn-on signal being in its on state when said first input signal is in its on state and said first lockout signal is in its non-lockout state;

a second driver turn-on signal having on and off states, said second driver turn-on signal being in its on state when said second input signal is in its on state and said second lockout signal is in its non-lockout state;

first and second driver circuits which receive said first and second driver turn-on signals at respective inputs and which produce first and second driver circuit outputs which have on and off states at respective outputs which track said first and second driver turn-on signals, said first and second driver circuit outputs, when in their on state, suitable for actuating first and second power devices which conduct respective currents when actuated;

a first predefined task which must be completed before said second power device is to be actuated;

a second predefined task which must be completed before said first power device is to be actuated;

a first state machine which provides said second lockout signal at an output, said first state machine arranged to monitor the status of said first predefined task and to toggle said second lockout signal from its lockout state to its non-lockout state when said first predefined task is completed;

a second state machine which provides said first lockout signal at an output, said second state machine arranged to monitor the status of said second predefined task and to toggle said first lockout signal from its lockout state to its non-lockout state when said second predefined task is completed;

such that said first and second driver circuit outputs are prevented from being in their on states simultaneously.

2. The control circuit of claim 1, wherein said first predefined task comprises detecting that said first driver circuit output toggled from its on state to its off state and said second predefined task comprises detecting that said second driver circuit output toggled from its on state to its off state.

3. An anti-cross conduction driver control circuit, comprising:

first and second normally complementary input signals, each of which has on and off states;

a first logic gate connected to receive said first input signal and a first lockout signal at respective inputs and arranged to provide a first driver turn-on signal having on and off states, said first lockout signal having lockout and non-lockout states, said first logic gate arranged to set said first driver turn-on signal to its on state when said first-lockout signal is in its non-lockout state and said first input signal is in its on state, and to set its first driver turn-on signal to its off state otherwise;

a second logic gate connected to receive said second input signal and a second lockout signal at respective inputs and arranged to provide a second driver turn-on signal having on and off states, said second lockout signal having lockout and non-lockout states, said second logic gate arranged to set its second driver turn-on signal to its on state when said second lockout signal is in its non-lockout state and said second input signal is in its on state, and to set its second driver turn-on signal to its off state otherwise;

a first driver circuit having an input connected to receive said first driver turn-on signal and an output having on and off states, said first driver circuit output tracking said first driver turn-on signal, said first driver circuit output, when in said on state, suitable for actuating a first power device which conducts a current when actuated;

a second driver circuit having an input connected to receive said second driver turn-on signal and an output having on and off states, said second driver circuit output tracking said second driver turn-on signal, said second driver circuit output, when in said on state, suitable for actuating a second power device which conducts a current when actuated;

a first state machine which receives said first driver turn-on signal and said first driver circuit output at respective inputs and which provides said second lockout signal at an output, said first state machine arranged to toggle said second lockout signal from its non-lockout state to its lockout state when said first driver turn-on signal toggles from its off state to its on state, and to toggle said second lockout signal from its lockout state to its non-lockout state when said first driver circuit output toggles from its on state to its off state, and

a second state machine which receives said second driver turn-on signal and said second driver circuit output at respective inputs and which provides said first lockout signal at an output, said second state machine arranged to toggle said first lockout signal from its non-lockout state to its lockout state when said second driver turn-on signal toggles from its off state to its on state, and to toggle said first lockout signal from its lockout state to its non-lockout state when said second driver circuit output toggles from its on state to its off state,

such that said first and second driver circuit outputs are prevented from being in their on states simultaneously.

4. The control circuit of claim 3, wherein said logic gates are AND gates and said on and off states are “

high” and

“

low”

logic levels, respectively.

5. The control circuit of claim 3, further comprising first and second power devices which conduct respective currents in response to said first and second driver circuit outputs, respectively.

6. The control circuit of claim 5, wherein said first and second power devices are field-effect transistors having their drain-source circuits connected in series.

7. The control circuit of claim 3, wherein each of said state machines is arranged to:

transfer from a first state (S0) in which said state machine'"'"'s lockout signal is in said non-lockout state to a second state (S1) in which said lockout signal is in said lockout state when the driver turn-on signal provided to said state machine toggles from off to on;

transfer from state S1 to a third state (S2) in which said lockout signal is in said lockout state when the driver circuit output provided to said state machine toggles from off to on; and

transfer from state S2 to state S0 when the driver circuit output provided to said state machine toggles from on to off, thereby toggling said lockout signal from its lockout state to its non-lockout state.

8. The control circuit of claim 7, wherein each of said state machines is further arranged to:

remain in state S1 if the driver turn-on signal provided to said state machine toggles from off to on while said state machine is in state S1; and

transfer from state S2 to state S1 if the driver turn-on signal provided to said state machine toggles from off to on while said state machine is in state S2.

9. The control circuit of claim 7, wherein at least one of said state machines is further arranged to:

generate a timeout signal which toggles from on to off when said driver turn-on signal provided to said state machine toggles from off to on and toggles from off to on a predetermined time period after said driver turn-on signal provided to said state machine toggles from on to off,

said state machine arranged to transfer from state S1 to state S2 when said timeout signal toggles from off to on or when the driver circuit output provided to said state machine toggles from off to on.

10. The control circuit of claim 9, wherein at least one of said at least one state machines is further arranged to transfer from state S2 to state S0 when said timeout signal toggles from off to on or when the driver circuit output provided to said state machine toggles from on to off.

11. The control circuit of claim 7, further comprising control logic which receives a plurality of input terms and outputs said first and second normally complementary input signals based on said input terms.

12. An anti-cross conduction driver control circuit, comprising:

first and second power devices which conduct respective currents when actuated in response to first (DRVH) and second (DRVL) driver circuit outputs, respectively;

control logic which receives a plurality of input terms and which outputs a first input signal (IN) which attains a “

high”

logic level when said first power device is to be actuated and a “

low”

logic level otherwise, and a second input signal ({overscore (IN)}) which is normally complementary to said first input signal which attains a “

high”

logic level when said second power device is to be actuated and a “

low”

logic level otherwise;

a first AND gate connected to receive IN and a first lockout signal (Loff) having “

low” and

“

high”

logic states at respective inputs and arranged to provide a first driver turn-on signal (Hto) wherein Hto={overscore (IN)}·

Loff;

a second AND gate connected to receive {overscore (IN)} and a second lockout signal (Hoff) having “

low” and

“

high”

logic states at respective inputs and arranged to provide a second driver turn-on signal (Lto) wherein Lto={overscore (IN)}·

Hoff;

a first driver circuit having an input connected to receive Hto and an output (DRVH) which tracks Hto, said DRVH output when “

high”

actuating said first power device;

a second driver circuit having an input connected to receive Lto and an output (DRVL) which tracks Lto, said DRVL output when “

high”

actuating said second power device;

a first state machine which receives Hto and DRVH at respective inputs and which provides Hoff at an output, said first state machine arranged to toggle Hoff from “

high”

to “

low”

when Hto toggles from “

low”

to “

high”

, and to toggle Hoff from “

low”

to “

high”

when DRVH toggles from “

high”

to “

low”

, and

a second state machine which receives Lto and DRVL at respective inputs and which provides Loff at an output, said second state machine arranged to toggle Loff from “

high”

to “

low”

when Lto toggles from “

low”

to “

high”

, and to toggle Loff from “

low”

to “

high”

when DRVL toggles from “

high”

to “

low”

,

such that DRVH and DRVL are prevented from being “

high”

simultaneously, thereby preventing said first and second power devices from being actuated simultaneously.

13. The control circuit of claim 12, wherein said first and second power devices are field-effect transistors having their drain-source circuits connected in series.

14. The control circuit of claim 12, wherein each of said state machines is arranged to:

transfer from a first state (S0) in which said state machine'"'"'s lockout signal is “

high”

to a second state (S1) in which said lockout signal is “

low”

when the driver turn-on signal provided to said state machine toggles from “

low”

to “

high”

;

transfer from state S1 to a third state (S2) in which said lockout signal is “

low”

when the driver circuit output provided to said state machine toggles from “

low”

to “

high”

;

transfer from state S2 to state S0 when the driver circuit output provided to said state machine toggles from “

high”

to “

low”

, thereby toggling said lockout signal from “

low”

to “

high”

;

remain in state S1 if the driver turn-on signal provided to said state machine toggles from “

low”

to “

high”

while said state machine is in state S1; and

transfer from state S2 to state S1 if the driver turn-on signal provided to said state machine toggles from “

low”

to “

high”

while said state machine is in state S2.

15. The control circuit of claim 14, wherein at least one of said state machines is further arranged to:

generate a timeout signal {overscore (tod)} which toggles from “

high”

to “

low”

when said driver turn-on signal provided to said state machine toggles from “

low”

to “

high” and

toggles from “

low”

to “

high”

a predetermined time period after said driver turn-on signal provided to said state machine toggles from “

high”

to “

low”

,

said state machine arranged to transfer from state S1 to state S2 when {overscore (tod)} toggles from “

low”

to “

high”

or when the driver circuit output provided to said state machine toggles from “

low”

to “

high”

.

16. The control circuit of claim 14, wherein said second state machine comprises:

a first logic gate arranged to produce an output Q1={double overscore (Lto)}{overscore (·

P1)};

a second logic gate arranged to produce an output Q0={double overscore (Q1)}{overscore (·

P0)};

a third logic gate arranged to produce an output P0={overscore (DRVL·

Q0)}; and

a fourth logic gate arranged to produce an output P1={double overscore (tod)}{overscore (·

P0·

Q1)};

said output Q0={overscore (Loff)}.

17. A method of preventing cross-conduction between first and second series-connected power devices which conduct respective currents when actuated in response to first and second drive signals, respectively, which are in turn responsive to first and second input signals which are normally complementary, comprising:

gating a first input signal having on and off states with a first lockout signal;

buffering said gated first input signal such that it tracks said gated first input signal, said buffered gated first input signal being said first drive signal, said first drive signal suitable for actuating said first power device when in said on state;

gating a second input signal which is normally complementary to said first input signal with a second lockout signal;

buffering said gated second input signal such that it tracks said gated second input signal, said buffered gated second input signal being said second drive signal, said second drive signal suitable for actuating said second power device when in said on state;

monitoring said gated first input signal and said first drive signal;

setting said second lockout signal to allow said second input signal to pass when said first drive signal toggles from said on state to said off state and setting said second lockout signal to block said second input signal when said gated first input signal toggles from its off state to its on state; and

setting said first lockout signal to block said first input signal when said gated second input signal toggles from its off state to its on state and setting said first lockout signal to allow said first input signal to pass when said second drive signal toggles from said on state to said off state.

18. The method of claim 17, wherein said step of setting said first lockout signal to allow said first input signal to pass further requires first detecting that said first drive signal has toggled from its off state to its on state.