Array oscillator and polyphase clock generator
First Claim
1. A differential buffer stage configured to receive differential signals at input signal ports (IN_P, IN_N) and to provide complementary buffer stage outputs at output ports (O_P, O_N), comprising:
- a first (51) and second (52) load elements, connected with their gates to a load control voltage (VT), for controlling the amplitude of output signals (O_P, O_N), each load element including at least one N-type MOSFET transistor (51, 52) for converting current into voltage;
at least one static current source (50) to which is applied a static current source bias (VJ), at least one pair of switch transistors (53, 54);
wherein the buffer stage is controlled by at least one set of two voltages, including static load control voltage, VT, and static bias control voltage, VJ, where VT depends on VJ and is derived from this voltage by the use of a replica bias circuitry.
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Abstract
The present invention relates generally to array oscillator circuits for use as phase delay generators. More particularly, the present invention relates to a novel array oscillator for providing a plurality of phases which have stable phase relationships. The present invention is particularly applicable to the generation of poly-phase clocks for receivers of very high speed interfaces which employ an over-sampling technique, or multiplexing, and for high speed logic. The array oscillator according to the invention comprises at least one ring oscillator having a plurality of at least two interconnected buffer stages including at least one, or any integer odd number of inverting stages and a series of non-inverting stages, wherein the buffer stages are formed of N-type MOSFET transistors.
163 Citations
52 Claims
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1. A differential buffer stage configured to receive differential signals at input signal ports (IN_P, IN_N) and to provide complementary buffer stage outputs at output ports (O_P, O_N), comprising:
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a first (51) and second (52) load elements, connected with their gates to a load control voltage (VT), for controlling the amplitude of output signals (O_P, O_N), each load element including at least one N-type MOSFET transistor (51, 52) for converting current into voltage;
at least one static current source (50) to which is applied a static current source bias (VJ), at least one pair of switch transistors (53, 54);
wherein the buffer stage is controlled by at least one set of two voltages, including static load control voltage, VT, and static bias control voltage, VJ, where VT depends on VJ and is derived from this voltage by the use of a replica bias circuitry. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 19, 20, 21, 22, 26, 30, 31, 35, 41, 42, 43, 47, 48, 49, 51)
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18. A differential buffer stage configured to receive differential signals at input signal ports (IN_P1, IN_N1) and input coupling ports (IN_P0, IN_N0) and to provide complementary buffer stage outputs at output ports (O_P, O_N) comprising:
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first (21, 22) and second (26, 27) load elements, connected respectively to first, static, and second, dynamic, load voltages (VT, VT1) for controlling the amplitude of output signals (O_P, O_N), each load element including a set of N-type MOSFET transistors (21, 22 and 26, 27), for converting current into voltage;
wherein transistors (26,27) are connected in parallel with the drains of transistors (21,22), for dynamic modulation of the load of the differential stage;
a static current source (20) and a dynamic current source (29) to which are applied, respectively, a static and dynamic current source biases (VJ and VJ1), two pairs of switch transistors (23, 25, 24, 28);
the drains of the load transistors (21, 22 and 26, 27) being connected through switch transistors (23, 24, 25, 26) to the current source transistors (20, 29) controlled by current source biases VJ and VJ1;
wherein the buffer stage is controlled by two sets of voltages, including load control voltages VT,VT1 and bias control voltages VJ, VJ1, where VT(VT1) depends on VJ(VJ1) and is derived from these voltages by the use of a replica bias circuitry. - View Dependent Claims (32, 36)
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23. A replica bias circuitry for providing control voltages for controlling a high speed differential buffer stage formed of NMOS elements, the circuitry comprising:
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a cascade of at least one load transistor (102) and at least one transistor (104) acting as a current source, a source (105) of a reference voltage, an operational amplifier (106) having one input connected to the reference voltage and another input connected to the source of transistor (102);
a transistor (107) having its gate connected to a supply voltage (VDD) and source connected to the output of the amplifier (106); and
a resistor (108) connected in series between an input voltage VIN and the gates of the load transistor (102);
wherein a control voltage (VJ) is supplied to the transistor current source (104) to provide a current flowing in the said cascade of transistors (102, 104), a load voltage (VT) is supplied to the gates of the said load transistor (102) and is further coupled to resistor 108; and
the difference between a voltage drop in the load transistor (102) and the reference voltage being amplified by the operational amplifier (106) to control a load voltage (VT) through a feedback formed of said transistor (107) and resistor (108). - View Dependent Claims (24, 25, 27, 28, 29, 34, 40, 44, 45, 46, 50, 52)
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33. A ring oscillator circuit comprising a plurality of at least two interconnected buffer stages including at least one, or any integer odd number of inverting stages and a series of non-inverting stages, such that there is a 180 degrees phase shift or odd multiple thereof through the ring oscillator,
wherein each buffer stage comprises a set of load elements so that at least one load element is formed of N-type MOSFET transistors; - the load elements being connected to control voltages for controlling the amplitude of output signals, and connected through switch transistors to current source transistors controlled by current source biases for controlling the frequency of output signals.
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37. An array oscillator circuit comprising:
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a plurality of at least two ring oscillators, each ring oscillator having a plurality of at least two interconnected buffer stages including at least one, or any integer odd number of inverting stages and a series of non-inverting stages, such that there is a 180 degrees phase shift or odd multiple thereof through the ring oscillator, wherein each buffer stage comprises a set of load elements so that at least one load element is formed of N-type MOSFET transistors;
the load elements being connected to control voltages for controlling the amplitude of output signals, and connected through switch transistors to current source transistors controlled by current source biases for controlling the frequency of output signals. - View Dependent Claims (38, 39)
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Specification