High bandwidth high gain receiver equalizer

• US 20060001504A1
• Filed: 06/13/2005
• Published: 01/05/2006
• Est. Priority Date: 06/14/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Singh, Bhajan, Ward, Richard, Pickering, Andrew
• Granted Patent: US 7,562,108 B2
• Time in Patent Office: Days
• US Class Current: 333/28.R
• CPC Class Codes: H03H 11/1291 Current or voltage controlled filters
• CPC Class Codes: H04L 25/03878 Line equalisers; line build-out devices

Abstract

There is provided a receiver equalizer comprising, a first equalizer unit having a basic equalizer stage and a negative impedance cell connected to said basic equalizer stage. Preferably the negative impedance cell comprises a pair of back to back transistors, and connected thereto a parallel resistor capacitor RC network. The basic equalizer stage comprises: a pair of current sources; a pair of transistors arranged as a differential pair, each transistor connected to a different one of the current sources; and a degeneration impedance connected in between the two current sources, and the transistors, wherein the negative impedance cell is connected across the outputs of the pair of transistors.

Claims

1. A receiver equalizer comprising, a first equalizer unit having a basic equalizer stage;

and

a negative impedance cell connected to said basic equalizer stage.

2. A receiver equalizer according to claim 1 wherein the negative impedance cell comprises a pair of back to back transistors, and connected thereto a parallel resistor capacitor RC network.

3. A receiver equalizer according to claim 1 wherein the basic equalizer stage comprises:

a pair of current sources;

a pair of transistors arranged as a differential pair, each transistor connected to a different one of the current sources; and

a degeneration impedance connected in between the two current sources, and the transistors,

wherein the negative impedance cell is connected across the outputs of the pair of transistors.

4. A receiver equalizer according to claim 3 wherein the degeneration impedance comprises two capacitors, one connected in parallel to each current source

5. A receiver equalizer according to claim 3 wherein the degeneration impedance comprises a parallel resistance capacitance RC network connected between the two current sources.

6. A receiver equalizer according to claim 3 wherein the negative impedance cell comprises a pair of back to back transistors, and connected thereto, a parallel resistor capacitor RC network.

7. A receiver equalizer according to claim 6 further comprising a second equalizer stage, wherein said first equalizer unit is cascaded from said second equalizer stage.

8. A receiver equalizer according to claim 6 further comprising a second equalizer unit cascaded from said first equalizer unit, said second equalizer unit comprising a further equalizer stage and a negative impedance cell connected thereto.

9. A receiver equalizer according to claim 7 wherein the second equalizer stage and the first equalizer stage are identical.

10. A receiver equalizer according to claim 8 wherein the first equalizer unit and the second equalizer unit are identical.

11. A method of applying equalization at a receiver, comprising the steps of:

providing a basic equalizer stage; and

applying a negative impedance to the basic equalizer stage.

12. A method according to claim 11, comprising:

cascading the basic equalizer stage from a second equalizer stage.