Frame buffer pixel circuit for liquid crystal display

• US 20060001634A1
• Filed: 06/24/2005
• Published: 01/05/2006
• Est. Priority Date: 11/07/2002
• Status: Active Grant

• Current Assignee: Duke University
• Original Assignee: Duke University
• Inventors: Morizio, James C., Lee, Sangrok, Johnson, Kristina M.
• Granted Patent: US 7,460,101 B2
• Time in Patent Office: Days
• US Class Current: 345/98
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0847 being a dynamic memory without any storage capacitor, i.e. with use of parasitic capacitances as storage elements
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 2310/0259 with use of an analog or digital ramp generator in the column driver or in the pixel circuit
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 3/2014 by modulation of the duration of a single pulse during which the logic level remains constant
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

An enhanced frame buffet pixel circuit with two control transistors and a separate capacitor put in as a memory capacitor before the memory transistor yields a high contrast ratio by removing induced charge and solving a charge sharing problem between the memory capacitor and the liquid crystal display (LCD) capacitor. The memory transistor may be made of either CMOS or PMOS. The frame buffer pixel can be used to drive binary displays which expresses ON and OFF only if a comparator is put in after the pixel electrode circuit to represent gray levels with reduced sub-frame frequency.

Claims

1. A circuit for controlling a pixel electrode of a display, comprising:

an amplification circuitry having an input and an output;

a first controller enabled by a first control signal to store a first analog data signal containing pixel data in a first storage unit either coupled to the input of the amplification circuitry, or formed by a parasitic capacitance present between the input and the output of the amplification circuitry;

a second controller enabled by a second control signal to couple the output of the amplification circuitry to a second storage unit thereby storing a second analog data signal proportional to the first analog data signal in the second storage unit; and

the second storage unit directly coupled to a pixel electrode to control a pixel value corresponding to the second analog data signal;

the amplification circuitry and the second controller provide isolation between the first storage unit and the second storage unit.

2. The circuit of claim 1, wherein the first storage unit is comprised of either a first capacitor consisting of a voltage independent capacitor, a gate capacitor of the amplification circuitry, or a combination of a voltage independent capacitor and a gate capacitor of the amplification circuitry.

3. The circuit of claim 1, wherein the second storage unit is a second capacitor comprised of a voltage independent capacitor.

4. The circuit of claim 2, wherein:

the second storage unit is a second capacitor comprised of a voltage independent capacitor; and

the first and second capacitors can be independently optimized to hold the first analog data signal and the second analog data signal, respectively, for one sub-frame time.

5. The circuit of claim 2, wherein the first capacitor as a voltage independent capacitor, or the second storage unit comprise a planar or trench capacitor comprising a dielectric layer between two metal layers.

6. The circuit of claim 2, wherein the first capacitor is a gate capacitor and is comprised from the group consisting of:

at least one N-channel field effect transistor, at least one P-channel field effect transistor, or one N-channel field effect transistor and one P-channel field effect transistor.

7. The circuit of claim 1, wherein the first controller is comprised from the group consisting of:

at least one N-channel field effect transistor or at least one P-channel field effect transistor, or a pass gate that combines an N-channel field effect transistor and a P-channel field effect transistor.

8. The circuit of claim 1, wherein the second controller comprises a field effect transistor, or a pass gate that combines an N-channel field effect transistor and a P-channel field effect transistor.

9. The circuit of claim 1, further comprising a drain unit coupled to the second storage unit to drain voltage from the second storage unit before the pixel value is transferred to the pixel electrode.

10. The circuit of claim 1, further comprising:

an analog to pulse width modulation (PWM) converter coupled between the second storage unit and the pixel electrode;

wherein the PWM converter modulates the second analog data signal with a reference signal having a period to control the amount of on and off time of the voltage of the second analog data signal applied to the pixel electrode during the period.

11. The circuit of claim 10, wherein the reference voltage is comprised of a wave form that does not have an inflection point thereby causing the second analog data signal to be switched only one time during the period.

12. The circuit of claim 10, wherein the reference voltage is varied by applying gamma correction.

13. The circuit of claim 1, wherein charge induction from the first storage unit to the second storage unit does not affect the voltage of the second analog data signal by more than 1 Volt.

14. A circuit for controlling a pixel electrode of a display, comprising:

an amplification circuitry having an input and an output;

a first controller enabled by a first control signal to store a first analog data signal containing pixel data in a first storage unit coupled to the input of the amplification circuitry; and

a second controller enabled by a second control signal to activate the amplification circuitry to charge a second storage unit with a second analog data signal in proportion to the first analog data signal stored in the first storage unit;

the second storage unit coupled directly to a pixel electrode to control a pixel value corresponding to the second analog data signal.

15. The circuit of claim 14, wherein the first storage unit is a first capacitor, the second storage unit is a second capacitor, and the first and second capacitors are independently optimized to hold the first analog data signal and the second analog data signal, respectively, for one sub-frame time.

16. The circuit of claim 14, wherein the first storage unit or the second storage unit comprises a planar or trench capacitor comprising a dielectric layer between two metal layers.

17. The circuit of claim 14, wherein the amplification circuitry is comprised from the group consisting of:

at least one N-channel field effect transistor, at least one P-channel field effect transistor, or one N-channel field effect transistor and one P-channel field effect transistor.

18. The circuit of claim 14, wherein the first controller is comprised from the group consisting of:

at least one N-channel field effect transistor or at least one P-channel field effect transistor, or a pass gate that combines an N-channel field effect transistor and a P-channel field effect transistor.

19. The circuit of claim 14, wherein the second controller comprises a field effect transistor, or a pass gate that combines an N-channel field effect transistor and a P-channel field effect transistor.

20. The circuit of claim 14, further comprising a drain unit coupled to the second storage unit to drain voltage from the second storage unit before the pixel value is transferred to the pixel electrode.

21. The circuit of claim 14,

an analog to pulse width modulation (PWM) converter coupled between the second storage unit and the pixel electrode;

wherein the PWM converter modulates the second analog data signal with a reference signal having a period to control the amount of on and off time of the voltage of the second analog data signal applied to the pixel electrode during the period.

22. The circuit of claim 21, wherein the reference voltage is comprised of a wave form that does not have an inflection point thereby causing the second analog data signal to be switched only one time during a period.

23. The circuit of claim 21, wherein the reference voltage is varied by applying gamma correction.

24. The circuit of claim 14, wherein charge induction from the first storage unit to the second storage unit does not affect the voltage of the second analog data signal by more than 1 Volt.

25. A circuit for controlling a pixel electrode of a display, comprising:

a first controller enabled by a first control signal to store a first analog data signal containing pixel data in a first storage unit;

a second controller enabled by a second control signal to charge a second storage unit with a second analog data signal in proportion to the first analog data signal stored in the first storage unit; and

an analog to pulse width modulation (PWM) converter coupled between the second storage unit and the pixel electrode;

wherein the PWM converter modulates the second analog data signal with a reference signal having a period to control the amount of on and off time of the voltage of the second analog data signal applied to the pixel electrode during the period; and

wherein the reference voltage is comprised of a wave form that does not have an inflection point thereby causing the second analog data signal to be switched only one time during a period.

26. The circuit of claim 25, wherein the reference voltage is varied by applying gamma correction.

27. A method of controlling a pixel electrode of a display, comprising the steps of:

generating a first control signal;

storing a first analog data signal containing pixel data in a first storage unit either coupled to an amplification circuitry or formed by the parasitic capacitance of the amplification circuitry, in response to the first control signal;

generating a second control signal to a control unit which is coupled to an output of the amplification circuitry;

charging a second storage unit with a second analog data signal provided by the control unit in proportion to the first analog data signal stored in the first storage unit in response to the second control signal;

isolating the first storage unit and the second storage unit using the amplification circuitry; and

controlling a pixel value corresponding to the second analog data signal coupled to a pixel electrode in the display that is directly coupled to the second storage unit.

28. A method of controlling a pixel electrode of a display, comprising the steps of:

generating a first control signal;

storing a first analog data signal containing pixel data in a first storage unit coupled to an input of an amplification circuitry in response to the first control signal;

generating a second control signal;

activating the amplification circuitry to charge a second storage unit with a second analog data signal in proportion to the first analog data signal stored in the first storage unit in response to the second control signal; and

controlling a pixel value corresponding to the second analog data signal on a pixel electrode in the display that is directly coupled to the second storage unit.

29. A method of controlling a pixel electrode of a display, comprising the steps of:

generating a first control signal;

storing a first analog data signal containing pixel data in a first storage unit in response to the first control signal;

generating a second control signal;

charging a second storage unit with a second analog data signal in proportion to the first analog data signal stored in the first storage unit in response to the second control signal;

generating a modulation reference signal having a period wherein the reference signal does not have an inflection point over the entire period;

modulating the second analog data signal with the reference signal having a period to generate a pulse width modulated (PWM) signal comprised of the second analog data signal switch on only once per period as a result of the reference signal not having an inflection point; and

applying the PWM signal to the pixel electrode to control the amount of on and off time of the voltage of the second analog data signal applied to a pixel electrode during the period.