Method and apparatus to detect invalid data in a nonvolatile memory following a loss of power
First Claim
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1. A method, comprising:
- setting at least one power loss recovery (PLR) status bit in response to the writing to or erasing of a plurality of nonvolatile memory cells of a nonvolatile memory, wherein the at least one PLR status bit indicates whether the writing to or erasing of the plurality of memory cells was interrupted by a loss of power and wherein the setting of the at least one PLR status bit is performed by the nonvolatile memory.
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Abstract
Briefly, in accordance with an embodiment of the invention, a method and apparatus to detect invalid data in a memory is provided. The method may include setting at least one power loss recovery (PLR) status bit in response to the writing to or erasing of a plurality of nonvolatile memory cells of a nonvolatile memory, wherein the at least one PLR status bit indicates whether the writing to or erasing of the plurality of memory cells was interrupted by a loss of power and wherein the setting of the at least one PLR status bit is performed by the nonvolatile memory. Other embodiments are described and claimed.
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Citations
23 Claims
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1. A method, comprising:
setting at least one power loss recovery (PLR) status bit in response to the writing to or erasing of a plurality of nonvolatile memory cells of a nonvolatile memory, wherein the at least one PLR status bit indicates whether the writing to or erasing of the plurality of memory cells was interrupted by a loss of power and wherein the setting of the at least one PLR status bit is performed by the nonvolatile memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A nonvolatile memory, comprising:
a control circuit to set at least one power loss recovery (PLR) status bit in response to a write operation or an erase operation to a plurality of nonvolatile memory cells of the nonvolatile memory, wherein the at least one PLR status bit indicates whether the write operation or the erase operation was interrupted by a loss of power and wherein the at least one PLR status bit is set by the control circuit of the nonvolatile memory. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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19. A system, comprising:
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a processor;
an antenna coupled to the processor; and
a flash electrically erasable programmable read-only memory (EEPROM) coupled to the processor, wherein the flash EEPROM comprises a control circuit to set at least one power loss recovery (PLR) status bit in response to a write operation or an erase operation to a plurality of memory cells of the flash EEPROM, wherein the at least one PLR status bit indicates whether the write operation or the erase operation was interrupted by a loss of power and wherein the at least one PLR status bit is set by the control circuit of the flash EEPROM. - View Dependent Claims (20, 21)
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22. A method, comprising:
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setting at least one power loss recovery (PLR) status bit in response to the writing to a plurality of nonvolatile memory cells of a nonvolatile memory, wherein the at least one PLR status bit indicates whether the writing to the plurality of memory cells was interrupted by a loss of power and wherein the setting of the at least one PLR status bit is performed by the nonvolatile memory; and
receiving an address of the plurality of nonvolatile memory cells from the nonvolatile memory. - View Dependent Claims (23)
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Specification