Method for improving a semiconductor device delamination resistance

• US 20060003572A1
• Filed: 07/03/2004
• Published: 01/05/2006
• Est. Priority Date: 07/03/2004
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lu, Yung-Cheng, Bao, Tien-I, Jang, Syun-Ming, Chang, Hui-Lin, Li, Lih-Ping, Lin, Keng-Chu, Chen, Pi-Tsung
• Granted Patent: US 7,456,093 B2
• Time in Patent Office: Days
• US Class Current: 438/622
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/3192 Multilayer coating
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device with improved resistance to delamination and method for forming the same the method including providing a semiconductor wafer comprising a metallization layer with an uppermost etch stop layer; forming at least one adhesion promoting layer on the etch stop layer; and, forming an inter-metal dielectric (IMD) layer on the at least one adhesion promoting layer.

Claims

1. A method for forming a multi-level integrated circuit semiconductor device with improved resistance to delamination comprising the steps of:

providing a semiconductor wafer comprising a metallization layer with an uppermost etch stop layer;

forming at least one adhesion promoting layer on the etch stop layer; and

,

forming an inter-metal dielectric (IMD) layer on the at least one adhesion promoting layer.

2. The method of claim 1, wherein the adhesion promoting layer comprises an atomic substituent common to both the IMD layer and the etch stop layer.

3. The method of claim 2, wherein the atomic substituent comprises an atomic concentration gradient increasing in a direction toward the IMD layer.

4. The method of claim 2, wherein the adhesion promoting layer comprises multiple layers each layer sequentially increasing in atomic concentration of the atomic substituents in a direction toward the IMD layer.

5. The method of claim 2, wherein the atomic substituent is selected from the group consisting of silicon, nitrogen, and oxygen.

6. The method of claim 1, wherein the adhesion promoting layer comprises the same atomic substituents as the etch stop layer in addition to an increased atomic oxygen concentration.

7. The method of claim 1, wherein the transition layer is selected from the group consisting of silicon oxynitride, oxygen doped silicon carbide, and nitrogen doped silicon carbide.

8. The method of claim 1, wherein the etch stop layer is selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbide, oxygen doped silicon carbide, and nitrogen doped silicon carbide.

9. The method of claim 1, wherein the etch stop layer and the adhesion promoting layer are formed in-situ by a PECVD process.

10. The method of claim 1, wherein the adhesion promoting layer and the IMD layer are formed in-situ by a PECVD process.

11. The method of claim 1, wherein the IMD layer comprises silicon oxide.

12. The method of claim 1, wherein the IMD layer is selected from the group consisting of carbon doped oxide and organo-silicate glass (OSG).

13. The method of claim 1, wherein the adhesion promoting layer is formed by an oxidizing plasma process on the first etch stop layer.

14. The method of claim 1, wherein the adhesion promoting layer is formed by a chemical oxidizing plasma process on the first etch stop layer.

15. The method of claim 1, wherein the adhesion promoting layer comprises an intervening IMD layer formed over the etch stop layer having a dielectric constant higher than the IMD layer.

16. The method of claim 1, further comprising forming a stress adjustable passivation layer over an uppermost metallization layer comprising bonding pads.

17. The method of claim 16, wherein the stress adjustable passivation layer is formed with a stress level comprising a stress type one of tensile and compressive to counteract a stress type and level present in underlying metallization layers.

18. The method of claim 16, further comprising the step of forming a stress transition layer comprising a stress level intermediate between the uppermost metallization layer and the stress adjustable passivation layer interposed between the respective layers.

19. The method of claim 18, wherein the stress adjustable passivation layer and the stress transition layer are selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbide, oxygen doped silicon carbide, and nitrogen doped silicon carbide.

20. The method of claim 16, further comprising the steps of:

forming a chip;

forming a first layer of molding material adjacent the chip having a first coefficient of thermal expansion (CTE); and

,

forming a second layer of molding material on the first layer of molding material having a second CTE larger than the first CTE.

21. The method of claim 20, wherein the first layer comprises a filler material having a higher thermal conductivity compared to filler material for the second layer.

22. The method of claim 20, wherein the first layer comprises a material having a higher volume of porosity with respect to an arbitrary volume of the material compared to the second layer.

23. A method for forming a multi-level integrated circuit semiconductor device with improved resistance to delamination comprising the steps of:

providing a semiconductor wafer comprising a metallization layer with an uppermost etch stop layer;

forming at least one adhesion promoting layer on the etch stop layer;

forming an IMD layer on the at least one adhesion promoting layer; and

,

forming a stress adjustable passivation layer over an uppermost metallization layer comprising bonding pads.

24. A method for forming a multi-level integrated circuit semiconductor device with improved resistance to delamination comprising the steps of:

providing a semiconductor wafer comprising a metallization layer with an uppermost etch stop layer;

forming at least one adhesion promoting layer on the etch stop layer;

forming an IMD layer on the at least one adhesion promoting layer;

forming a stress adjustable passivation layer over an uppermost metallization layer comprising bonding pads;

forming a chip;

forming a first layer of molding material adjacent the chip having a first coefficient of thermal expansion (CTE); and

,

forming a second layer of molding material on the first layer of molding material having a second CTE larger than the first CTE.

25. A semiconductor device with improved resistance to delamination comprising:

a chip comprising an adhesion promoting layer interposed between an etch stop layer and an inter-metal dielectric (IMD) layer.

26. The semiconductor device of claim 25, wherein the adhesion promoting layer comprises an atomic substituent common to both the IMD layer and the etch stop layer.

27. The semiconductor device of claim 26, wherein the atomic substituent comprises an atomic concentration gradient increasing in a direction toward the IMD layer.

28. The semiconductor device of claim 26, wherein the adhesion promoting layer comprises multiple layers each layer sequentially increasing in atomic concentration of the atomic substituent in a direction toward the IMD layer.

29. The semiconductor device of claim 26, wherein the atomic substituent is selected from the group consisting of silicon, nitrogen, and oxygen.

30. The semiconductor device of claim 25, wherein the adhesion promoting layer comprises the same atomic substituents as the etch stop layer in addition to an increased atomic oxygen concentration.

31. The semiconductor device of claim 25, wherein the transition layer is selected from the group consisting of silicon oxynitride, nitrogen doped silicon carbide, and oxygen doped silicon carbide.

32. The semiconductor device of claim 25, wherein the etch stop layer is selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbide, nitrogen doped silicon carbide, and oxygen doped silicon carbide.

33. The semiconductor device of claim 25, wherein the IMD layer comprises silicon oxide.

34. The semiconductor device of claim 25, wherein the IMD layer is selected from the group consisting of carbon doped oxide and organo-silicate glass (OSG).

35. The semiconductor device of claim 25, wherein the adhesion promoting layer comprises an intervening IMD layer formed over the etch stop layer having a dielectric constant higher than the IMD layer.

36. The semiconductor device of claim 25, further comprising a stress adjustable passivation layer overlying an uppermost metallization layer comprising bonding pads.

37. The semiconductor device of claim 36, wherein the stress adjustable passivation layer has a stress level comprising a stress type one of tensile and compressive to counteract a stress type and level present in underlying metallization layers.

38. The semiconductor device of claim 36, further comprising a stress transition layer comprising a stress level intermediate between the uppermost metallization layer and the stress adjustable passivation layer interposed between the respective layers.

39. The semiconductor device of claim 36, wherein the stress adjustable passivation layer and the stress transition layer are selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbide, and oxygen doped silicon carbide.

40. The semiconductor device of claim 25, further comprising:

a first layer of molding material adjacent the chip having a first coefficient of thermal expansion (CTE); and

,

a second layer of molding material on the first layer of molding material having a second CTE larger than the first CTE.

41. The semiconductor device of claim 40, wherein the first layer comprises a filler material having a higher thermal conductivity compared to filler material for the second layer.

42. The semiconductor device of claim 40, wherein the first layer comprises a material having a higher volume of porosity with respect to an arbitrary volume of the material compared to the second layer.

43. A semiconductor device with improved resistance to delamination comprising:

a chip comprising an adhesion promoting layer interposed between an etch stop layer and an inter-metal dielectric (IMD) layer; and

,

a stress adjustable passivation layer over an uppermost metallization layer comprising bonding pads.

44. A semiconductor device with improved resistance to delamination comprising:

a chip comprising an adhesion promoting layer interposed between an etch stop layer and an inter-metal dielectric (IMD) layer;

a stress adjustable passivation layer over an uppermost metallization layer comprising bonding pads;

a first layer of molding material adjacent the chip having a first coefficient of thermal expansion (CTE); and

,

a second layer of molding material on the first layer of molding material having a second CTE larger than the first CTE.