Artificial neuron with phase-encoded logic

• US 20060004681A1
• Filed: 04/29/2005
• Published: 01/05/2006
• Est. Priority Date: 04/29/2004
• Status: Active Grant

• Current Assignee: University Of Massachusetts
• Original Assignee: University Of Massachusetts
• Inventors: Michel, Howard E., Rancour, David P.
• Granted Patent: US 7,401,058 B2
• Time in Patent Office: Days
• US Class Current: 706/26
• CPC Class Codes: G06N 3/049 Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
• CPC Class Codes: G06N 3/065 Analogue means

Abstract

An artificial neuron includes an aggregator that combines a plurality of input signals. The value state of each of the input signals is encoded in a phase thereof. The artificial neuron also includes an actuator in communication with the aggregator. The actuator is configured to provide an output signal having a value state encoded in a phase thereof. The value state of the output signal may be selected on the basis of the value states of the input signals. The value state of each of the input signals and/or the output signal may be a logical state.

Claims

1. An artificial neuron comprising:

an aggregator that combines a plurality of input signals, the value state of each of the input signals being encoded in a phase thereof; and

an actuator in communication with the aggregator, the actuator configured to provide an output signal, the value state of the output signal encoded in a phase thereof, the value state of the output signal being selected on the basis of the value states of the input signals.

2. The neuron of claim 1, wherein the aggregator comprises a plurality of delay elements, wherein each of plurality of delay elements applies a corresponding phase delay to one of the plurality of input signals.

3. The neuron of claim 2, further comprising:

a bias input that receives a bias signal;

a bias input delay element in communication with the bias input that applies a bias phase delay to the bias signal.

4. The neuron of claim 2, wherein the aggregator further comprises a summer that adds the plurality of input signals.

5. The neuron of claim 3, wherein the aggregator further comprises a summer that adds the plurality of input signals, and the bias signal.

6. The neuron of claim 1, wherein the actuator comprises:

a threshold detector configured to provide a detector output, the detector output indicating whether a sum of the plurality of input signals exceeds a threshold, and

a multiplexer that selects, on the basis of the detector output, an output signal from among a plurality of mutually phase-shifted signals.

7. The neuron of claim 1, wherein the value state of each of the input signals is a logical state, and wherein the value state of the output signal is a logical state.

8. A circuit for implementing the neuron of claim 1.

9. The circuit of claim 8, wherein the circuit is a CMOS circuit.

10. The circuit of claim 8, wherein the plurality of input signals includes a first and second input, and wherein the aggregator comprises a differential amplifier that receives the first and second inputs and provides a difference thereof.

11. The circuit of claim 10, wherein the actuator comprises:

a rectifier that receives a difference signal from the differential amplifier, and

a Schmitt trigger having an output state controlled by an output of the rectifier.

12. The circuit of claim 8, wherein the aggregator comprises a summation circuit that receives the plurality of input signals and provides an output current corresponding to the sum of the respective currents produced by the plurality of input signals.

13. The circuit of claim 12, wherein the actuator comprises:

a rectifier that rectifies the output received from the summation circuit,

a DC-level shifter that shifts the DC component of the signal rectified by the rectifier, and

an inverter chain that determines if the rectified and DC-shifted signal exceeds a threshold value associated with the inverter chain.

14. The circuit of claim 11, wherein the rectifier includes at least one of:

a full-wave rectifier, and a half-wave rectifier.

15. An artificial neuron comprising:

an aggregator that combines a plurality of continuous input signals, the value state of each of the input signals being encoded in at least one of;

a phase of the corresponding input signal, an amplitude of the corresponding input signal, and a frequency of the corresponding input signal; and

an actuator in communication with the aggregator, the actuator configured to provide a continuous output signal, the value state of the output signal encoded in at least one of;

a phase of the output signal, an amplitude of the output signal, and a frequency of the output signal, the value state of the output signal being selected on the basis of the value states of the input signals.

16. The neuron of claim 15, wherein the aggregator comprises a plurality of delay elements, wherein each of plurality of delay elements applies a corresponding phase delay to one of the input signals.

17. The neuron of claim 16, further comprising:

a bias input that receives a continuous bias signal;

a bias input delay element in communication with the bias input that applies a bias phase delay to the bias signal.

18. The neuron of claim 16, wherein the aggregator further comprises a summer that adds the plurality of input signals.

19. The neuron of claim 17, wherein the aggregator further comprises a summer that adds the plurality of input signals, and the bias signal.

20. The neuron of claim 15, wherein the actuator comprises:

a threshold detector configured to provide a detector output, the detector output indicating whether a sum of the plurality of input signals exceeds a threshold, and

a multiplexer that selects, on the basis of the detector output, a continuous output signal from among a plurality of mutually phase-shifted continuous signals.

21. A method for processing data using an artificial neuron, the method comprising:

receiving, at the artificial neuron, a plurality of input signals, the value state of each of the input signals encoded in a phase thereof,

combining the plurality of input signals, and

providing a neuron output signal, the value state of the neuron output signal encoded in a phase thereof, the value state of the neuron output signal selected on the basis of the value states of the input signals.

22. The method of claim 21, wherein combining comprises applying a phase delay to at least one of the plurality of input signals.

23. The method of claim 22 further comprising:

receiving a continuous bias signal, and

applying a bias phase delay to the bias signal.

24. The method of claim 22, wherein combining further comprises adding the plurality of input signals together.

25. The method of claim 23, wherein combining further comprises adding together the plurality of input signals and the bias signal.

26. The method of claim 21, wherein providing comprises:

generating a threshold output indicating whether a sum of the input signals exceeds a threshold, and

selecting, on the basis of the threshold value, the neuron output signal from a plurality of mutually phase-shifted continuous signals.

27. The method of claim 21, wherein the value state of each of the input signals is a logical state, and wherein the value state of the neuron output signal is a logical state.

28. A system comprising a plurality of interconnected artificial neurons, each of the artificial neurons including:

an aggregator that combines a plurality of continuous input signals, the value state of each of the input signals being encoded in a phase thereof; and

an actuator in communication with the aggregator, the actuator configured to provide a continuous output signal, the value state of the output signal being encoded in a phase thereof, and being selected on the basis of the value states of the input signals.

29. The system of claim 28, wherein the aggregator comprises a plurality of delay elements, each of which applies a corresponding phase delay to one of the plurality of input signals.

30. The system of claim 29, further comprising:

a bias input that receives a continuous bias signal; and

a bias input delay element, in communication with the bias input, that applies a bias phase delay to the bias signal.

31. The system of claim 29, wherein the aggregator further comprises a summer that adds the plurality of input signals together.

32. The system of claim 30, wherein the aggregator further comprises a summer that adds together the plurality of input signals and the bias signal.

33. The system of claim 28, wherein the actuator comprises:

a threshold detector configured to provide a detector output, the detector output indicating whether a sum of the plurality of input signals exceeds a threshold, and

a multiplexer that selects, on the basis of the detector output, a continuous output signal from among a plurality of mutually phase-shifted continuous signals.

34. The system of claim 28, wherein the value state of each of the input signals represents a logical state, and wherein the value state of the output signal represents a logical state.

35. A method of manufacturing artificial neurons, the method comprises forming, for each artificial neuron:

a) an aggregator that combines a plurality of continuous input signals, the value state of each of the input signals being encoded in a phase thereof; and

b) an actuator in communication with the aggregator, the actuator configured to provide a continuous output signal, the value state of the output signal encoded in a phase thereof, the value state of the output signal being selected on the basis of the value states of the input signals.

36. The method of claim 35, wherein the aggregator comprises a plurality of delay elements, wherein each of plurality of delay elements applies a corresponding phase delay to one of the plurality of input signals.

37. The method of claim 36, wherein the artificial neuron further comprises a bias delay element that applies a bias phase delay to a continuous bias signal.

38. The method of claim 36, wherein the aggregator further comprises a summer that adds the plurality of input signals.

39. The method of claim 37, wherein the aggregator further comprises a summer that adds the plurality of input signals, and the bias signal.

40. The method of claim 35, wherein the actuator comprises:

a threshold detector configured to provide a detector output, the detector output indicating whether a sum of the plurality of input signals exceeds a threshold, and

a multiplexer that selects, on the basis of the detector output, a continuous output signal from among a plurality of mutually phase-shifted continuous signals.

41. The method of claim 35, wherein the value state of each of the input signals is a logical state, and wherein the value state of the output signal is a logical state.