Method of managing a multi-bit-cell flash memory

• US 20060004952A1
• Filed: 08/08/2005
• Published: 01/05/2006
• Est. Priority Date: 02/15/2004
• Status: Active Grant

• Current Assignee: Western Digital Israel Limited (Western Digital Corporation)
• Original Assignee: M-Systems Flash Disk Pioneers Ltd. (Western Digital Corporation)
• Inventors: Lasser, Menahem
• Granted Patent: US 7,716,413 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 2211/5646 Multilevel memory with flag bits, e.g. for showing that a "first page" of a word line is programmed but not a "second page"

Abstract

A flash memory is managed by reserving one or more cells as flag cells to represent the number N of bits to store in the cells of a memory block, selecting the value of N from at least three candidates, and programming the flag cell(s) to represent the selected value. A flash memory is managed by selecting a value of the number N>2 of bits to store in the cells of a portion (e.g. a block or page) of the memory, reserving one other cell of the memory as a flag cell to represent how many bits actually are stored in each cell of the portion, and, as the cells of the portion are successively programmed with 1≦n≦N bits, programming the flag cell to represent n.

Claims

1. A method of managing a flash memory, comprising the steps of:

(a) reserving at least one cell of the flash memory to use as a flag cell to represent a value of a number N of bits of data to store in each of a plurality of other cells of a block of the flash memory;

(b) selecting a value of N from among at least three candidate values of N; and

(c) programming said at least one flag cell to represent said selected value of N.

2. The method of claim 1, further comprising the step of:

(d) programming said plurality of other cells to represent said data in accordance with said selected value of N.

3. The method of claim 1, wherein only one said flag cell is reserved.

4. The method of claim 1, wherein a plurality of said flag cells are reserved, and wherien all said flag cells are programmed identically to represent said selected value of N.

5. The method of claim 1, wherein said value of N is selected from among only three candidate values thereof.

6. The method of claim 1, wherein said value of N is selected from among four candidate values thereof.

7. A memory device comprising:

(a) a flash memory including at least one block, each said at least one block including a plurality of cells; and

(b) a flash memory controller operative, for one of said at least one block;

(i) to reserve at least one cell of said one block to use as a flag cell to represent a value, of a number N of bits of data to store in a plurality of other cells of said one block,

(ii) to select a value of N from among at least three candidate values of N, and

(iii) to program said at least one flag cell to represent said selected value of N.

8. The memory device of claim 7, wherein said flash memory controller is operative to reserve only one said flag cell for said one block.

9. The memory device of claim 7, wherein said flash memory controller is operative to reserve a plurality of said flag cells for said one block and to program all said flag cells identically to represent said selected value of N.

10. The memory device of claim 7, wherein said flash memory controller is operative to select said value of N from among only three candidate values thereof.

11. The memory device of claim 7, wherein said flash memory controller is operative to select said value of N from among four candidate values thereof.

12. A system comprising:

(a) a flash memory including at least one block, each said at least one block including a plurality of cells;

(b) a non-volatile memory for storing program code for, for one of said at least one block;

(i) reserving at least one cell of said one block to use as a flag cell to represent a value, of a number N of bits of data to store in a plurality of other cells of said one block,

(ii) selecting a value of N from among at least three candidate values of N, and

(iii) programming said at least one flag cell to represent said selected value of N; and

(c) a processor for executing said program code.

13. The system of claim 12, wherein said program code is for reserving only one said cell of said one block to use as said flag cell.

14. The system of claim 12, wherein said program code is for reserving a plurality of said cells of said one block to use as said flag cells and for prgramming all said flag cells identically to represent said selected value of N.

15. The system of claim 12, wherein said program code is for selecting said value of N from among only three candidate values thereof.

16. The system of claim 12, wherein said program code is for selecting said value of N from among four candidate values thereof.

17. A computer-readable storage medium having computer-readable code embedded on the computer-readable storage medium, the computer-readable code for managing a flash memory that includes at least one block, each at least one block including a plurality of cells, the computer-readable code comprising program code for, for one of the at least one block:

(a) reserving at least one cell of the one block to use as a flag cell to represent a value, of a number N of bits of data to store in a plurality of other cells of the one block;

(b) selecting a value of N from among at least three candidate values of N; and

(c) programming said at least one flag cell to represent said selected value of N.

18. The computer-readable storage medium of claim 17, wherein said program code is for reserving only one said cell of the one block to use as said flag cell.

19. The computer-readable storage medium of claim 17, wherein said program code is for reserving a plurality of said cells of the one block to use as said flag cells and for programming all said flag cells identically to represent said selected value of N.

20. The computer-readable storage medium of claim 17, wherein said program code is for selecting said value of N from among only three candidate values thereof.

21. The computer-readable storage medium of claim 17, wherein said program code is for selecting said value of N from among four candidate values thereof.

24. The method of claim 18, wherein only one said flag storage element is reserved.

25. The method of claim 18, wherein a plurality of said flag storage elements are reserved and wherein all said flag storage elements are set identically to represent said selected value of N.

22. A method of managing a non-volatile array of storage elements individually having a storage window divisible into a plurality of defined ranges of storage levels representative of N≧

1 bits and which are separated from one another, the method comprising the steps of;

(a) reserving at least one storage element to use as a flag storage element to represent a value of N for each of a plurality of other storage elements of at least a portion of the non-volatile array;

(b) selecting a value of N from among at least three candidate values of N; and

(c) setting said at least one flag storage element to represent said selected value of N.

23. The method of claim 22, further comprising the step of:

(d) programming said plurality of other storage elements to represent data in accordance with said selected value of N.

26. The method of claim 22, wherein said value of N is selected from among only three candidate values thereof.

27. The method of claim 22, wherein said value of N is selected from among four candidate values thereof.

28. A memory device comprising:

(a) a non-volatile array of storage elements individually having a storage window divisible into a plurality of defined ranges of storage levels representative of N≧

1 bits and which are separated from one another; and

(b) a controller for;

(i) reserving at least one said storage element to use as a flag storage element to represent a value of N for each of a plurality of other said storage elements of at least a portion of the non-volatile array,

(ii) selecting a value of N from among at least three candidate values of N, and

(iii) setting said at least one flag storage element to represent said selected value of N.

29. The memory device of claim 28, wherein said flash memory controller is operative to reserve only one said flag storage element for said at least portion.

30. The memory device of claim 28, wherein said flash memory controller is operative to reserve a plurality of said flag storage elements for said at least portion and to set all said flag storage elements identically to represent said selected value of N.

31. The memory device of claim 28, wherein said flash memory controller is operative to select said value of N from among only three candidate values thereof.

32. The memory device of claim 28, wherein said flash memory controller is operative to select said value of N from among four candidate values thereof.

33. A system comprising:

(a) a non-volatile array of storage elements individually having a storage window divisible into a plurality of defined ranges of storage levels representative of N≧

1 bits and which are separated from one another;

(b) a non-volatile memory for storing program code for;

(i) reserving at least one said storage element to use as a flag storage element to represent a value of N for each of a plurality of other said storage elements of at least a portion of the non-volatile array;

(ii) selecting a value of N from among at least three candidate values of N, and

(iii) setting said at least one flag storage element to represent said selected value of N; and

(c) a processor for executing said program code.

34. The system of claim 33, wherein said program code is for reserving only one said storage element to use as said flag storage element.

35. The system of claim 33, wherein said program code is for reserving a pluralty of said storage elements to use as said flag storage elements and to set all said flag storage elements identically to represent said selected value of N.

36. The system of claim 33, wherein said program code is for selecting said value of N from among only three candidate values thereof.

37. The system of claim 33, wherein said program code is for selecting said value of N from among four candidate values thereof.

38. A computer-readable storage medium having computer-readable code embedded on the computer-readable storage medium, the computer-readable code for managing a non-volatile array of storage elements individually having a storage window divisible into a plurality of defined ranges of storage levels representative of N≧

1 bits and which are separated from one another, the computer-readable code comprising;

(a) program code for reserving at least one storage element to use as a flag storage element to represent a value of N for each of a plurality of other storage elements of at least a portion of the non-volatile array;

(b) program code for selecting a value of N from among at least three candidate values of N, and

(c) program code for setting said at least one flag storage element to represent said selected value of N.

39. The computer-readable storage medium of claim 38, wherein said program code is for reserving only one said storage element to use as said flag storage element.

40. The computer-readable storage medium of claim 38, wherein said prgram code is for reserving a plurality of said storage elements to use as said flag storage element and to set all said flag storage elements identically to represent said selected value of N.

41. The computer-readable storage medium of claim 38, wherein said program code is for selecting said value of N from among only three candidate values thereof.

42. The computer-readable storage medium of claim 38, wherein said program code is for selecting said value of N from among four candidate values thereof.

43. A method of managing a flash memory, comprising the steps of:

(a) selecting a value of a number N≧

3 of respective bits of data to be stored in each of a plurality of cells of at least a portion of a flash memory;

(b) reserving a single other cell of the flash memory to use as a flag cell to represent a value of how many of said N bits are stored in each said cell of said plurality; and

(c) successively, for each value of n between 1 and N;

(i) programming each said cell of said plurality to represent a first respective n bits of said data, and

(ii) programming said flag cell to represent n.

44. The method of claim 43, wherein said at least portion of the flash memory is a block of the flash memory.

45. The method of claim 43, wherein said at least portion of the flash memory is a page of the flash memory.

46. The method of claim 43, wherein N is selected equal to 3.

47. The method of claim 43, wherein N is selected equal to 4.

48. A memory device comprising:

(a) a flash memory including at least one block, each said at least one block including at least one page, each said at least one page including a plurality of cells; and

(b) a flash memory controller operative, for a portion of said flash memory selected from the group consisting of one of said at least one block and one of said at least one page of one of said at least one block;

(i) to select a value of a number N≧

3 of respective bits of data to be stored in each of a plurality of cells of said portion,

(ii) to reserve a single other cell of said portion to use as a flag cell to represent a value of how many of said N bits are stored in each said cell of said plurality, and

(iii) successively, for each value of n between 1 and N;

(A) to program each said cell of said plurality to represent a first respective n bits of said data, and

(B) to program said flag cell to represent n.

49. The memory device of claim 48, wherein N=3.

50. The memory device of claim 48, wherein N=4.

51. A system comprising:

(a) a flash memory including at least one block, each said at least one block including at least one page, each said at least one page including a plurality of cells;

(b) a non-volatile memory for storing program code for, for a portion of said flash memory selected from the group consisting of one of said at least one block and one of said at least one page of one of said at least one block;

(i) selecting a value of a number N≧

3 of respective bits of data to be stored in each of a plurality of cells of said portion,

(ii) reserving a single other cell of said portion to use as a flag cell to represent a value of how many of said N bits are stored in each said cell of said plurality, and

(iii) successively, for each value of n between 1 and N;

(A) programming each said cell of said plurality to represent a first respective n bits of said data, and

(B) programming said flag cell to represent n; and

(c) a processor for executing said program code.

52. The system of claim 51, wherein N=3.

53. The system of claim 51, wherein N=4.

54. A computer-readable storage medium having computer-readable code embedded on the computer-readable storage medium, the computer-readable code for managing a flash memory that includes at least one block, each at least one block including at least one page, each at least one page including a plurality of cells, the computer-readable code comprising program code for, for a portion of the flash memory selected from the group consisting of one of the at least one block and one of the at least one page of one of the at least one block:

(a) selecting a value of a number N≧

3 of respective bits of data to be stored in each of a plurality of cells of the portion;

(b) reserving a single other cell of the portion to use as a flag cell to represent a value of how many of said N bits are stored in each cell of the plurality; and

(c) successively, for each value of n between 1 and N;

(i) programming each cell of the plurality to represent a first respective n bits of said data, and

(ii) programming said flag cell to represent n.

55. The computer-readable storage medium of claim 54, wherein N=3.

56. The computer-readable storage emdium of claim 54, wherein N=4.

57. A method of managing a non-volatile array of storage elements individually having a storage window divisible into a plurality of defined ranges of storage levels representative of at least one bit of data and which are separated from one another, the method comprising the steps of:

(a) selecting a number N≧

3 of bits to be represented by the defined ranges of the storage levels of each of a plurality of the storage elements of at least a portion of the non-volatile array;

(b) reserving a single other storage element to use as a flag storage element to represent a value of how many of the N bits are stored in each storage element of said plurality; and

(c) successively, for each value of n between 1 and N;

(i) setting each storage element of said plurality to represent a first respective n bits of the data, and

(ii) setting said flag storage element to represent n.

58. The method of claim 57, wherein N is selected equal to 3.

59. The method of claim 57, wherein N is selected equal to 4.

60. A memory device comprising:

(a) a non-volatile array of storage elements individually having a storage window divisible into a plurality of defined ranges of storage levels representative of at least one bit of data and which are separated from one another; and

(b) a controller for;

(i) selecting a number N≧

3 of bits to be represented by the defined ranges of the storage levels of each of a plurality of said storage elements of at least a portion of the non-volatile array,

(ii) reserving a single other said storage element to use as a flag storage element to represent a value of how many of said N bits are stored in each said storage element of said plurality, and

(iii) successively, for each value of n between 1 and N;

(A) setting each said storage element of said plurality to represent a first respective n bits of said data, and

(B) setting said flag storage element to represent n.

61. The memory device of claim 60, wherein N=3.

62. The memory device of claim 60, wherein N=4.

63. A system comprising:

(a) a non-volatile array of storage elements individually having a storage window divisible into a plurality of defined ranges of storage levels representative of at least one bit of data and which are separated from one another;

(b) a non-volatile memory for storing program code for;

(i) selecting a number N≧

3 of bits to be represented by the defined ranges of the storage levels of each of a plurality of said storage elements of at least a portion of said non-volatile array,

(ii) reserving a single other said storage element to use as a flag storage element to represent a value of how many of said N bits are stored in each said storage element of said plurality, and

(iii) successively, for each value of n between 1 and N;

(A) setting each said storage element of said plurality to represent a first respective n bits of said data, and

(B) setting said flag storage element to represent n; and

(c) a processor for executing said program code.

64. The system of claim 63, wherein N=3.

65. The system of claim 63, wherein N=4.

66. A computer-readable storage medium having computer-readable code embedded on the computer-readable storage medium, the computer-readable code for managing a non-volatile array of storage elements individually having a storage window divisible into a plurality of defined ranges of storage levels representative of at least one bit of data and which are separated from one another, the computer-readable code comprising:

(a) program code for selecting a number N≧

3 of bits to be represented by the defined ranges of the storage levels of each of a plurality of the storage elements of at least a portion of the non-volatile array;

(b) program code for reserving a single other storage element to use as a flag storage element to represent a value of how many of the N bits are stored in each said storage element of said plurality; and

(c) program code for successively, for each value of n between 1 and N;

(i) setting each said storage element of said plurality to represent a first respective n bits of said data, and

(ii) setting said flag storage element to represent n.

67. The computer-readable storage medium of claim 66, wherein N=3.

68. The computer-readable storage medium of claim 66, wherein N=4.