Semiconductor devices having a metal-insulator-metal capacitor and methods of forming the same

• US 20060006447A1
• Filed: 07/12/2005
• Published: 01/12/2006
• Est. Priority Date: 07/12/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Ki-Nam, Kim, Hyun-Ho, Joo, Heung-Jin
• Granted Patent: US 7,495,311 B2
• Time in Patent Office: Days
• US Class Current: 257/308
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H01L 28/65 comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
• CPC Class Codes: H01L 28/75 comprising two or more layers, e.g. comprising a barrier layer and a metal layer
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
• CPC Class Codes: H10B 53/30 characterised by the memory core region

Abstract

A semiconductor device having an MIM capacitor and a method of forming the same are provided. A lower electrode includes a plate electrode and a sidewall electrode. The plate electrode is formed by a patterning process preferably including a plasma anisotropic etching. The sidewall electrode is formed like a spacer on an inner sidewall of an opening exposing the plate electrode by a plasma entire surface anisotropic etching.

Claims

1. A semiconductor device including an MIM capacitor, comprising:

a plate electrode disposed on a substrate;

a mold layer covering the substrate and having an opening that exposes the plate electrode;

a sidewall electrode disposed on an inner sidewall of the opening like a spacer, electrically connecting the plate electrode; and

a dielectric pattern and an upper electrode that sequentially cover the plate electrode and the sidewall electrode in the opening,

wherein the plate electrode and the sidewall electrode compose a lower electrode.

2. The device of claim 1, wherein the lower electrode comprises a noble metal.

3. The device of claim 1, wherein at least an upper portion of the mold layer is a growth-promote insulation layer,

wherein the growth-promote insulation layer is an insulation layer that promotes a growth of the dielectric pattern.

4. The device of claim 1, further comprising:

a lower interlayer insulation layer interposed between the substrate and the mold layer;

a contact plug that penetrates the lower interlayer insulation layer to contact the substrate; and

an oxygen barrier pattern interposed between the contact plug and the plate electrode,

wherein the oxygen barrier pattern is formed of conductive materials.

5. The device of claim 1, further comprising:

a hydrogen diffusion barrier layer that is an insulation layer covering the upper electrode and the dielectric pattern.

6. The device of claim 1, wherein the upper electrode has a line shape in a plane view.

7. The device of claim 1, wherein the upper electrode has an island shape in a plan view and further comprises:

an upper interlayer insulation layer covering an entire surface of the upper electrode and having a plate contact hole exposing the upper electrode; and

a plate line disposed on the upper interlayer insulation layer and connected to the upper electrode via the plate contact hole.

8. A method of forming a semiconductor device having an MIM capacitor, comprising:

forming a plate electrode on a substrate;

forming a mold layer covering an entire surface of the substrate and having an opening exposing the plate electrode;

forming a second conductive layer conformally on an entire surface of substrate including a surface within the opening;

forming a spacer-shaped sidewall electrode on an inner sidewall of the opening by applying a plasma entire surface anisotropic etching to the second conductive layer; and

forming sequentially a dielectric pattern and an upper electrode that cover the plate electrode and the sidewall electrode in the opening,

wherein the plate electrode and the sidewall electrode compose a lower electrode.

9. The method of claim 8, wherein the lower electrode includes noble metals.

10. The method of claim 8, wherein at least an upper portion of the mold layer is a growth-promote insulation layer,

wherein the growth-promote insulation layer is an insulation layer that promote a growth of the dielectric pattern.

11. The method of claim 8, before forming the first conductive layer, further comprising:

forming a lower interlayer insulation layer on the substrate;

forming a contact plug contacting the substrate via the lower interlayer insulation layer; and

forming an oxygen barrier layer of a conductive material layer covering the contact plug,

wherein the forming of the plate electrode includes forming the oxygen barrier pattern and the plate electrode, which are sequentially stacked on the contact plug, by patterning successively the oxygen barrier layer and the conductive material layer using the plasma anisotropic etching.

12. The method of claim 8, after forming the upper electrode further comprising:

forming a hydrogen diffusion barrier layer covering the upper electrode and the dielectric pattern,

wherein the hydrogen diffusion barrier layer is formed of an insulation layer.

13. The method of claim 8, wherein the upper electrode is formed to have a line shape in a plan view.

14. The method of claim 8, wherein the upper electrode is formed to have an island shape in a plane view and further comprises after the forming of the upper electrode:

forming an upper interlayer insulation layer covering an entire surface of the substrate having the upper electrode;

forming a plate contact hole exposing the upper electrode by patterning the upper interlayer insulation layer; and

forming a plate line on the upper interlayer insulation layer, the plate line connected to the upper electrode via the plate contact hole.

15. The method of claim 8, wherein the plate electrode is formed by applying a patterning process including an anisotropic etching of a first conductive layer.