Electrically alterable memory cell

• US 20060006454A1
• Filed: 05/02/2005
• Published: 01/12/2006
• Est. Priority Date: 07/01/2004
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Wang, Chih-Hsin
• Granted Patent: US 7,759,719 B2
• Time in Patent Office: Days
• US Class Current: 257/314
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A nonvolatile memory cell is provided. The cell has a charge filter, a tunneling gate, a ballistic gate, a charge storage layer, a source, and a drain with a channel defined between the source and drain. The charge filter permits transporting of charge carriers of one polarity type from the tunneling gate through the blocking material and the ballistic gate to the charge storage layer while blocking the transport of charge carriers of an opposite polarity from the ballistic gate to the tunneling gate. Further embodiments of the present invention provide a cell having a charge filter, a supplier gate, a tunneling gate, a ballistic gate, a source, a drain, a channel, and a charge storage layer. The present invention further provides an energy band engineering method permitting the memory cell be operated without suffering from disturbs, from dielectric breakdown, from impact ionization, and from undesirable RC effects.

Claims

1. A nonvolatile memory cell, comprising:

a body of a semiconductor material having a first conductivity type;

a first and a second spaced-apart regions formed in the body and having a second conductivity type, with a channel region of the body defined therebetween;

a charge storage layer disposed over and insulated from the channel region;

a ballistic gate disposed over and insulated from the charge storage layer; and

a tunneling gate disposed over and insulated from the ballistic gate by a charge filter, wherein the charge filter permits transporting of charge carriers of one polarity type from the tunneling gate through the ballistic gate to the charge storage layer and blocks transporting of charge carriers of an opposite polarity type from the ballistic gate to the tunneling gate.

2. The memory cell of claim 1, wherein the charge filter comprises:

a first dielectric disposed adjacent to the ballistic gate; and

a second dielectric disposed adjacent to the first dielectric, wherein the first dielectric has an energy band gap narrower than the second dielectric.

3. The memory cell of claim 2, wherein the product of the dielectric constant of the first dielectric to the thickness of the second dielectric is substantially greater than the product of the dielectric constant of the second dielectric to the thickness of the first dielectric.

4. The memory cell of claim 2, wherein the second dielectric comprises oxide, and the first dielectric comprises material selected from the group consisting of nitride, oxynitride, Al₂O₃, HfO₂, TiO₂, ZrO₂, Ta₂O₅, and alloys formed thereof.

5. The memory cell of claim 2, wherein the second dielectric comprises oxynitride, and the first dielectric comprises material selected from the group consisting of nitride, Al₂O₃, HfO₂, TiO₂, ZrO₂, Ta₂O₅, and alloys formed thereof.

6. The memory cell of claim 2, wherein the tunneling gate comprises p+ semiconductor and the ballistic gate comprises n+ semiconductor having an energy band gap narrower than that of the first dielectric.

7. The memory cell of claim 2, wherein the ballistic gate has a Fermi level that in a flat band condition lies nominally in the middle of the energy band gap of the first dielectric.

8. The memory cell of claim 1, wherein the tunneling gate emits hole carriers when positively biased with respect to the ballistic gate, and emits electron carriers when negatively biased with respect to the ballistic gate.

9. The memory cell of claim 1, wherein the ballistic gate comprises material selected from the group consisting of Pt, Au, W, Mo, Ru, Ta, TaN, TiN, n+ polysilicon, p+ polysilicon, n+ poly SiGe and p+ poly SiGe.

10. The memory cell of claim 1, wherein the charge storage layer comprises polysilicon.

11. The memory cell of claim 1, wherein the charge storage layer comprises a plurality of spaced-apart nano-particles.

12. The memory cell of claim 11, wherein the nano-particles comprises material selected from the group consisting of Si, Ge, SiGe alloy, HfO₂, Au, Co, and W.

13. The memory cell of claim 1, wherein the charge storage layer comprises a dielectric having a plurality of charge storing traps.

14. The memory cell of claim 1, wherein the filter comprises:

a first dielectric disposed adjacent to the ballistic gate;

a blocking material disposed adjacent to the first dielectric; and

a second dielectric disposed adjacent to the blocking material, wherein the first dielectric has a narrower energy band gap than the second dielectric.

15. The memory cell of claim 14, wherein the first dielectric has a dielectric constant substantially higher than that of the second dielectric.

16. The memory cell of claim 14, wherein the product of the dielectric constant of the first dielectric to the thickness of the second dielectric is greater than the product of the dielectric constant of the second dielectric to the thickness of the first dielectric.

17. The memory cell of claim 14, wherein the blocking material comprises SiC.

18. The memory cell of claim 14, wherein the blocking material comprises a plurality of nano-crystals of a semiconductor material spaced apart from one another.

19. The memory cell of claim 14, wherein the tunneling gate comprises p+ semiconductor and the ballistic gate comprises n+ semiconductor having an energy band gap narrower than that of the blocking material.

20. A nonvolatile memory cell, comprising:

a body of a semiconductor material having a first conductivity type;

a first and a second spaced-apart regions formed in the body and having a second conductivity type, with a channel region of the body defined therebetween;

a charge storage layer disposed over and insulated from the channel region;

a ballistic gate of a first semiconductor material adjacent to a supplier gate of a second semiconductor material, wherein the ballistic gate and the supplier gate are disposed over the charge storage layer and the ballistic gate and the supplier gate have different energy band gaps and impurity concentrations; and

a tunneling gate disposed over and insulated from the most proximate of the ballistic gate and the supplier gate by a charge filter, wherein the charge filter permits transporting of charge carriers of one polarity type from the tunneling gate through the supplier gate and the ballistic gate to the charge storage layer and blocks transporting charge carriers of an opposite polarity type from the ballistic gate to the tunneling gate.

21. The memory cell of claim 20, wherein the supplier gate is heavily doped and the ballistic gate is un-doped or lightly doped of same type conductivity as the supplier gate, and wherein the ballistic gate has an energy band gap narrower than the supplier gate.

22. The memory cell of claim 21, wherein the charge filter comprises the supplier gate and a dielectric disposed adjacent thereto having an energy band gap wider than the supplier gate.

23. The memory cell of claim 22, wherein the supplier gate comprises SiC and the ballistic gate comprises polysilicon.

24. The memory cell of claim 20, wherein the charge filter comprises:

a first dielectric disposed over the supplier gate and the ballistic gate, and

a second dielectric disposed adjacent to the first dielectric and the tunneling gate, wherein the first dielectric has an energy band gap narrower than the second dielectric.

25. The memory cell of claim 24, wherein the supplier gate comprises polysilicon and the ballistic gate comprises poly SiGe.

26. The memory cell of claim 24, wherein the product of the dielectric constant of the first dielectric to the thickness of the second dielectric is greater than the product of the dielectric constant of the second dielectric to the thickness of the first dielectric.

27. The memory cell of claim 20, wherein the supplier gate is a first supplier gate, and further comprising:

a second supplier gate of a third semiconductor material having an energy band gap and impurity concentration different from the ballistic gate, wherein the ballistic gate is disposed in between the first supplier gate and the second supplier gate.

28. The memory cell of claim 27, wherein the first supplier gate and the second supplier gate are heavily doped and the ballistic gate is un-doped or lightly doped of same type conductivity, and wherein the ballistic gate has an energy band gap narrower than that of the first supplier gate and that of the second supplier gate.

29. The memory cell of claim 28, wherein the first supplier gate and the second supplier gate comprises polysilicon and the ballistic gate comprises poly SiGe.

30. The memory cell of claim 28, wherein the charge filter comprises:

the closest of the first supplier gate and the second supplier gate with respect to the tunneling gate; and

a dielectric disposed over the closest supplier gate and having an energy band gap wider than the closest supplier gate.

31. The memory cell of claim 27, wherein the ballistic gate is heavily doped and the first supplier gate and the second supplier gate are un-doped or lightly doped of same type conductivity, and wherein the ballistic gate has an energy band gap wider than that of the first supplier gate and that of the second supplier gate.

32. The memory cell of claim 31, wherein the first supplier gate and the second supplier gate comprises poly SiGe and the ballistic gate comprises polysilicon.

33. The memory cell of claim 27, wherein the charge filter comprises:

a first dielectric disposed adjacent to the most proximate of the first supplier gate and the second supplier gate, and

a second dielectric disposed adjacent to the first dielectric, wherein the first dielectric has an energy band gap narrower than the second dielectric.

34. The memory cell of claim 33, wherein the product of the dielectric constant of the first dielectric to the thickness of the second dielectric is greater than the product of the dielectric constant of the second dielectric to the thickness of the first dielectric.

35. The memory cell of claim 20, wherein the tunneling gate emits hole carriers when positively biased with respect to the ballistic gate, and emits electron carriers when negatively biased with respect to the ballistic gate.

36. A nonvolatile memory array having a plurality of memory cells arranged in rows and columns, each of the plurality of memory cells comprising:

a body of a semiconductor material having a first conductivity type;

a first and a second spaced-apart regions formed in the body and having a second conductivity type, with a channel region of the body defined therebetween;

a charge storage layer disposed over and insulated from the channel region;

a ballistic gate disposed over and insulated from the charge storage layer; and

a tunneling gate disposed over and insulated from the ballistic gate by a charge filter, wherein the charge filter permits transporting of charge carriers of one polarity type from the tunneling gate through the ballistic gate to the charge storage layer and blocks transporting of charge carriers of an opposite polarity type from the ballistic gate to the tunneling gate.