AC power supply apparatus, methods and computer program products using PWM synchronization

• US 20060006741A1
• Filed: 07/07/2004
• Published: 01/12/2006
• Est. Priority Date: 07/07/2004
• Status: Active Grant

• Current Assignee: Eaton Corp. (Wisconsin) (Eaton Corporation PLC.)
• Original Assignee: Eaton Corp. (Wisconsin) (Eaton Corporation PLC.)
• Inventors: Tassitino, Frederick Jr., Anderson, Jason S., Pfitzer, Hans-Erik, Westerfield, Michael
• Granted Patent: US 7,405,494 B2
• Time in Patent Office: Days
• US Class Current: 307/82
• CPC Class Codes: H02J 9/062 for AC powered loads
• CPC Class Codes: H02M 7/493 the static converters being arranged for operation in parallel

Abstract

Paralleled uninterruptible power supplies (UPSs) including respective pulse-width modulation (PWM) power converter circuits coupled in common to an AC load bus have PWM cycles that are synchronized. In particular, sampling of control inputs of the PWM power converter circuits may be synchronized, such that, for example, sampling of control inputs to the PWM power converter circuits occurs at substantially the same time for each of the PWM power converter circuits. A common phase reference corresponding to an AC voltage phase for the AC load bus may be provided, and the PWM cycles of each of the power converter circuits may synchronized, e.g., phase locked, to the common phase reference. More particularly, the respective PWM cycles of the UPSs may be phase locked to phase locked sinusoidal reference signals generated at each of the UPSs. Sampling for other control functions may also be synchronized to the PWM cycles.

Claims

1. A method of operating a plurality of paralleled uninterruptible power supplies (UPSs), the UPSs including respective pulse-width modulation (PWM) power converter circuits coupled in common to an AC load bus, the method comprising:

synchronizing PWM cycles of the PWM power converter circuits.

2. A method according to claim 1, wherein synchronizing PWM cycles of the PWM power converter circuits comprises synchronizing sampling of control inputs of the PWM power converter circuits.

3. A method according to claim 2, wherein synchronizing sampling of control inputs to the PWM power converter circuits comprises phase locking the PWM cycles such that sampling of control inputs to the PWM power converter circuits occurs at substantially the same time for each of the PWM power converter circuits.

4. A method according to claim 1, further comprising providing a phase reference corresponding to an AC voltage phase for the AC load bus, and wherein synchronizing PWM cycles of the PWM power converter circuits comprises synchronizing the PWM cycles of each of the power converter circuits to the phase reference.

5. A method according to claim 4:

wherein providing a phase reference comprises providing respective sinusoidal reference signals at respective ones of the UPSs; and

wherein synchronizing the PWM cycles of each of the power converter circuits to the phase reference comprises synchronizing the respective PWM cycles of the UPSs to the respective sinusoidal reference signals.

6. A method according to claim 5, further comprising determining respective power transfers at the common AC load bus for the respective UPSs, and wherein providing respective sinusoidal reference signals at respective ones of the UPSs comprises generating the respective sinusoidal reference signals responsive to the respective determined power transfers.

7. A method according to claim 5, wherein synchronizing the respective PWM cycles of the UPSs to the respective sinusoidal reference signals comprises:

determining a timing error of PWM cycles with respect to a sinusoidal reference signal; and

adjusting a PWM cycle duration responsive to the determined timing error.

8. A method according to claim 5, wherein synchronizing the respective PWM cycles of the UPSs to the respective sinusoidal reference signals comprises:

determining a number of PWM cycles occurring between phase indicia of a sinusoidal reference signal; and

adjusting a PWM cycle duration responsive to the determined number of PWM cycles.

9. A method according to claim 8, wherein the phase indicia comprise zero crossings of the sinusoidal reference signal.

10. A method according to claim 8:

wherein determining a number of PWM cycles occurring between phase indicia of a sinusoidal reference signal comprises;

determining a number of complete PWM cycles occurring between a first phase indicator of the sinusoidal reference signal and a second phase indicator of the sinusoidal reference signal; and

determining a fraction of a PWM cycle occurring between a phase indicator of a PWM cycle and the second phase indicator of the sinusoidal reference signal; and

wherein adjusting a PWM cycle duration responsive to the determined number of PWM cycles comprises adjusting the period of the PWM cycle based on the determined number of complete PWM cycles and the determined fraction of a PWM cycle.

11. A method according to claim 5, wherein synchronizing the respective PWM cycles of the UPSs to the respective sinusoidal reference signals comprises:

estimating a frequency error by comparing an actual angle step of a PWM cycle to a desired angle step;

estimating a zero crossing location of the sinusoidal reference signal with respect to a PWM cycle from discrete values of the sinusoidal reference signal;

estimating a phase error by comparing the estimated zero crossing location to a reference point of a PWM cycle; and

adjusting a PWM cycle duration responsive to the frequency error and the phase error.

12. A method according to claim 5, wherein providing respective sinusoidal reference signals at respective ones of the UPSs comprises providing a master sinusoidal reference signal to each of the UPSs.

13. A method according to claim 4, wherein at least one of the UPSs further includes an additional control circuit that samples an operating parameter of the at least one UPS and wherein the method further comprises synchronizing sampling of the operating parameter to the synchronized PWM cycles of the at least one UPS.

14. A method according to claim 13, wherein synchronizing sampling of the operating parameter to the synchronized PWM cycles of the at least one UPS comprises sampling input data for the PWM power converter circuit and the additional control circuit of the at least one UPS responsive to a common interrupt.

15. A method according to claim 13, wherein the operating parameter comprises an electrical quantity susceptible to a signal generated by at least one of the PWM power converter circuits on the common AC load bus.

16. A method according to claim 1, wherein the PWM power converter circuits comprise respective inverters having respective outputs coupled to the common AC load bus.

17. A system, comprising:

a plurality of paralleled UPSs, the UPSs including respective PWM power converter circuits coupled in common to an AC load bus and operating according to synchronized PWM cycles.

18. A system according to claim 17, wherein the UPSs have synchronized sampling of control inputs for their PWM converters.

19. A system according to claim 18, wherein the UPSs comprises means for phase locking their PWM cycles such that sampling of control inputs to their PWM power converter circuits occurs at substantially the same time.

20. A system according to claim 17, wherein the UPSs comprise means for synchronizing the PWM cycles of each of the power converter circuits to a phase reference corresponding to an AC voltage for the AC load bus.

21. A system according to claim 20, wherein the UPSs include respective means for generating respective sinusoidal reference signals, and respective means for synchronizing their respective PWM cycles their respective sinusoidal reference signals.

22. A system according to claim 21, wherein the UPSs comprise respective means for generating the respective sinusoidal reference signals responsive to respective power transfers thereof.

23. A system according to claim 21, wherein at least one of the UPSs comprises means for determining a timing error of PWM cycles of the at least one UPS with respect to the sinusoidal reference signal of the at least one UPS and for adjusting a PWM cycle duration of the at least one UPS responsive to the determined timing error.

24. A system according to claim 21, wherein at least one of the UPSs comprises means for determining a number of PWM cycles occurring between phase indicia of the sinusoidal reference signal of the at least one UPS and for adjusting a PWM cycle duration of the at least one UPS responsive to the determined number of PWM cycles.

25. A system according to claim 24, wherein the phase indicia comprise zero crossings of the sinusoidal reference signal.

26. A system according to claim 24, wherein the at least one of the UPSs comprises means for determining a number of complete PWM cycles occurring between a first phase indicator of the sinusoidal reference signal and a second phase indicator of the sinusoidal reference signal, for determining a fraction of a PWM cycle occurring between a phase indicator of a PWM cycle and the second phase indicator of the sinusoidal reference signal, and for adjusting a PWM cycle duration of the at least one UPS based on the determined number of complete PWM cycles and the determined fraction of a PWM cycle.

27. A system according to claim 21, wherein at least one of the UPSs comprises means for estimating a frequency error by comparing an actual angle step per PWM cycle to a desired angle step, for estimating a zero crossing location of the sinusoidal reference signal with respect to a PWM cycle from discrete values of the sinusoidal reference signal, for estimating a phase error by comparing the estimated zero crossing location to a reference point of a PWM cycle, and for adjusting a PWM cycle duration responsive to the frequency error and the phase error.

28. A system according to claim 21, wherein at least one of the UPSs further includes an additional control circuit that samples an operating parameter of the at least one UPS and wherein the at least one UPS is operative to synchronize sampling of the operating parameter to the synchronized PWM cycles of the at least one UPS.

29. A system according to Claim 28, wherein the at least on UPS is operative to sample input data for the PWM power converter circuit and the additional control circuit of the at least one UPS responsive to a common interrupt.

30. A system according to claim 28, wherein the operating parameter comprises an electrical quantity susceptible to a signal generated on the AC load bus by at least one of the PWM power converter circuits.

31. A system according to claim 17, wherein the PWM power converter circuits comprise respective inverters having outputs coupled to the common AC load bus.

32. An uninterruptible power supply (UPS), comprising:

a first PWM power converter circuit configured to be coupled to an AC load bus; and

a PWM cycle synchronizer circuit operative to synchronize PWM cycles of the PWM power converter circuit to PWM cycles of a second PWM power converter circuit coupled to the AC load bus.

33. A UPS according to claim 32, wherein the PWM cycle synchronizer circuit is operative to synchronize sampling of control inputs of the first PWM power converter circuit to sampling of control inputs for the second PWM power converter circuit.

34. A UPS according to claim 33, wherein the PWM cycle synchronizer circuit is operative to phase lock the PWM cycles of the first PWM power converter circuit to PWM cycles of the second PWM power converter circuit such that sampling of control inputs to the first and second PWM power converter circuits occurs at substantially the same time.

35. A UPS according to claim 32, wherein the PWM cycle synchronizer circuit is operative to synchronize the PWM cycles of the first PWM power converter circuit to a phase reference corresponding to an AC voltage for the AC load bus.

36. A UPS according to claim 35, further comprising a sinusoidal reference signal generator circuit operative to generate a sinusoidal reference signal, and wherein the PWM cycle synchronizer circuit is operative to synchronize the PWM cycles of the first PWM power converter circuit to the sinusoidal reference signal.

37. A UPS according to claim 36, further comprising a power determiner circuit operative to determine a power transfer for the first PWM power converter circuit at the AC load bus and wherein the sinusoidal reference signal generator circuit is operative to generate the sinusoidal reference signal responsive to the determined power transfer.

38. A UPS according to claim 36, wherein the PWM cycle synchronizer circuit is operative to determine a timing error of PWM cycles with respect to the sinusoidal reference signal and to adjust a PWM cycle duration responsive to the determined timing error.

39. A UPS according to claim 36, wherein the PWM cycle synchronizer circuit is operative to determine a number of PWM cycles occurring between phase indicia of the sinusoidal reference signal and to adjust a PWM cycle duration responsive to the determined number of PWM cycles.

40. A UPS according to claim 39, wherein the phase indicia comprise zero crossings of the sinusoidal reference signal.

41. A UPS according to claim 39, wherein the PWM cycle synchronizer circuit is operative to determine a number of complete PWM cycles occurring between a first phase indicator of the sinusoidal reference signal and a second phase indicator of the sinusoidal reference signal, to determine a fraction of a PWM cycle occurring between a phase indicator of a PWM cycle and the second phase indicator of the sinusoidal reference signal, and to adjust a PWM cycle duration based on the determined number of complete PWM cycles and the determined fraction of a PWM cycle.

42. A UPS according to claim 36, wherein the PWM cycle synchronizer circuit is operative to estimate a frequency error by comparing an actual angle step per PWM cycle to a desired angle step, to estimate a zero crossing location of the sinusoidal reference signal with respect to a PWM cycle from discrete values of the sinusoidal reference signal, to estimate a phase error by comparing the estimated zero crossing location to a reference point of a PWM cycle, and to adjust a PWM cycle duration responsive to the frequency error and the phase error.

43. A UPS according to claim 32, further comprising an additional control circuit that samples an operating parameter of the UPS and wherein the PWM synchronizer circuit is operative to synchronize sampling of the operating parameter to the synchronized PWM cycles.

44. A UPS according to claim 43, where the PWM synchronizer circuit generates a common interrupt for sampling input data for the PWM power converter circuit and the additional control circuit.

45. A UPS according to claim 43, wherein the operating parameter comprises an electrical quantity susceptible to a signal generated by the first PWM power converter circuit and/or the second PWM power converter circuit on the AC load bus.

46. A UPS according to claim 32, wherein the first PWM power converter circuit comprises an inverter having an output coupled to the AC load bus.

47. A computer program product for controlling a UPS having a first PWM power converter circuit configured to be coupled to an AC load bus, the computer program product comprising a computer readable storage medium having computer readable program code embodied therein, the computer readable program code comprising:

program code configured to synchronize PWM cycles of the PWM power converter circuit to PWM cycles of a second PWM power converter circuit coupled to the AC load bus.

48. A computer program product according to claim 47, wherein the program code configured to synchronize PWM cycles of the PWM power converter circuit to PWM cycles of a second PWM power converter circuit coupled to the AC load bus comprises program code configured to synchronize sampling of control inputs of the first and second PWM power converter circuits.

49. A computer program product according to claim 48, wherein the program code configured to synchronize sampling of control inputs of the first and second PWM power converter circuits comprises program code configured to phase lock the PWM cycles of the first and second PWM converters such that sampling of control inputs to the first and second PWM power converter circuits occurs at substantially the same time.

50. A computer program product according to claim 48, further comprising program code configured to generate a phase reference corresponding to an AC voltage phase for the AC load bus, and wherein the program code configured to synchronize PWM cycles of the PWM power converter circuit to PWM cycles of a second PWM power converter circuit coupled to the AC load bus comprises program code configured to phase lock the PWM cycles of the first PWM converter to the phase reference.

51. A computer program product according to claim 48, wherein the UPS includes an additional control circuit that samples an operating parameter of the UPS and wherein the program code configured to synchronize sampling of control inputs of the first and second PWM power converter circuits comprises program code configured to synchronize sampling of the operating parameter to the synchronized PWM cycles.