System and method for monitoring a charging period in a battery charger

• US 20060006843A1
• Filed: 07/09/2004
• Published: 01/12/2006
• Est. Priority Date: 07/09/2004
• Status: Active Grant

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Inventors: Wu, Zengjing
• Granted Patent: US 7,205,747 B2
• Time in Patent Office: Days
• US Class Current: 320/128
• CPC Class Codes: H02J 7/0068 Battery or charger load switching, e.g. concurrent charging and load supply H02J7/0013 takes precedence
• CPC Class Codes: Y10S 320/12 Precharging analysis, e.g. determining presence of battery

Abstract

An apparatus and method for disabling a charging counter circuitry within a battery charger is disclosed. The apparatus includes circuitry connected to a pin associated with the charging counter circuitry of the battery charger, said circuitry receiving a signal from a device connected to the battery charger. The circuitry disables the charging counter circuitry responsive to a signal from the device at a first level and enables the charging counter circuitry responsive to the signal from the device at a second level.

Claims

1. An apparatus for disabling charging counter circuitry within a battery charger, comprising:

circuitry connected to a pin associated with the charging counter circuitry of the battery charger and receiving a signal from a device connected to the battery charger, said circuitry disabling the charging counter circuitry responsive to the signal at a first level and enabling the charging counter circuitry responsive to the signal at a second level.

2. The apparatus of claim 1, wherein the signal at the first level indicates the device is being used.

3. The apparatus of claim 1, wherein the signal at the second level indicates the device is not being used.

4. The apparatus of claim 1, wherein the circuitry disables the charging counter by connecting the pin of the battery charger to ground.

5. The apparatus of claim 1, wherein the circuitry enables the charging counter by disconnecting the pin of the battery charger from ground.

6. The apparatus of claim 1, wherein the circuitry further comprises an NMOS transistor having a drain connected to the pin of the battery charger, having a source connected to ground and having a gate connected to receive the signal from the device.

7. An apparatus for disabling a charging counter circuitry within a battery charger, comprising:

a transistor having a drain connected to a pin associated with the charging counter circuitry of the battery charger, having a source connected to ground and having a gate connected to receive a signal from a device, said transistor disabling the charging counter circuitry by connecting the pin of the battery charger to the ground responsive to the signal at a first level and enabling the charging counter circuitry by disconnecting the pin of the battery charger from ground responsive to the signal at a second level.

8. The apparatus of claim 7, wherein the signal at the first level indicates the device is being used.

9. The apparatus of claim 7, wherein the signal at the second level indicates the device is not being used.

10. The apparatus of claim 7, wherein the transistor is an NMOS transistor.

11. A battery charger, comprising:

an input for receiving an input voltage;

first circuitry for providing a charge to a battery of a device connected to the battery charger;

second circuitry for counting a period of time the battery has been charging having a pin associated therewith; and

third circuitry connected to the pin of the second circuitry and receiving a signal from the device connected to the battery charger, said third circuitry disabling the second circuitry responsive to the signal at a first level and enabling the second circuitry responsive to the signal at a second level.

12. The battery charger of claim 11, wherein the signal at the first level indicates the device is being used.

13. The battery charger of claim 11, wherein the signal at the second level indicates the device is not being used.

14. The battery charger of claim 11, wherein the third circuitry disables the second circuitry by connecting the pin of the second circuitry to ground.

15. The battery charger of claim 11, wherein the third circuitry enables the second circuitry by disconnecting the pin of the second circuitry from ground.

16. The battery charger of claim 11, wherein the third circuitry further comprise a transistor having a drain connected to the pin of the battery charger, having a source connected to ground and having a gate connected to receive the signal from the device.

17. The apparatus of claim 16, wherein the transistor is an NMOS transistor.

18. A system, comprising:

a battery charger;

a device connected to the battery charger and generating a signal indicating wether the device is being used;

first circuitry within the battery charger for counting a period of time a battery associated with the device has been charging and having a pin associated therewith; and

second circuitry connected to the pin of the first circuitry and receiving the signal from the device connected to the battery charger, said second circuitry disabling the first circuitry responsive to the signal at a first level and enabling the first circuitry responsive to the signal at a second level.

19. The system of claim 18, wherein the signal at the first level indicates the device is being used.

20. The system of claim 18, wherein the signal at the second level indicates the device is not being used.

21. The system of claim 18, wherein the second circuitry disables the first circuitry by connecting the pin of the first circuitry to ground.

22. The system of claim 18, wherein the second circuitry enables the first circuitry by disconnecting the pin of the first circuitry from ground.

23. The system of claim 18, wherein the second circuitry further comprises a transistor having a drain connected to the pin of the battery charger, having a source connected to ground and having a gate connected to receive the signal from the device.

24. The system of claim 23, wherein the transistor is an NMOS transistor.

25. A method for counting a charging time of a battery associated with a battery charger, comprising the steps of:

receiving a use mode signal at a first level indicating a device connected to the battery charger is in use;

disabling circuitry counting a charging time of the battery responsive to the use mode signal at the first level;

receiving the use mode signal at a second level indicating a device connected to the battery charger is not in use; and

enabling the circuitry counting the charging time of the battery responsive to the use mode signal at the second level.

26. The method of claim 25, wherein the step of disabling further comprises the step of connecting the circuitry counting the charging time of the battery to ground.

27. The method of claim 25, wherein the step of enabling further comprises the step of disconnecting the circuitry counting the charging time of the battery from ground.