Dual panel pixel readout in an imager

• US 20060007337A1
• Filed: 07/12/2004
• Published: 01/12/2006
• Est. Priority Date: 07/12/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Panicacci, Roger
• Granted Patent: US 7,652,703 B2
• Time in Patent Office: Days
• US Class Current: 348/308
• CPC Class Codes: H04N 25/41 Extracting pixel data from a plurality of image sensors simultaneously picking up an image, e.g. for increasing the field of view by combining the outputs of a plurality of sensors
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/779 Circuitry for scanning or addressing the pixel array
• CPC Class Codes: H04N 25/7795 Circuitry for generating timing or clock signals
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

An imager having two panels of pixels (i.e., the imager'"'"'s rows of pixels are split into two panels) that are controllable by separate row decoders. The dual panel architecture allows pipelining of pixel readout and column readout operations to improve the imager'"'"'s frame rate. The dual panel architecture may use a standard pixel configuration, a shared column and/or a shared row and column configuration.

Claims

1. An imaging device comprising:

an array of pixels comprising first and second panels, each panel being organized into a plurality of rows and columns;

a first row decoder connected to the rows of said first panel;

a second row decoder connected to the rows of said second panel, said first and second row decoders being configured to respectively and independently activate rows within said first and second panels;

sample and hold circuitry connected to the columns of the first and second panels; and

a column decoder connected to said sample and hold circuitry, said column decoder being controlled to address said sample and hold circuitry such that pixel readout from the first and second panels and column readout of stored signals are pipelined.

2. The device of claim 1, wherein said pixels of each row are organized into pairs and each pair shares readout circuitry and a respective output line.

3. The device of claim 2 further comprising a plurality of multiplexers connected between the output lines and said sample and hold circuitry.

4. The device of claim 1, wherein said pixels in each row are organized into pairs, each pair of pixels in a first row is associated with a pair of pixels in an adjacent row and shares readout circuitry and a respective output line with the associated pair.

5. The device of claim 4 further comprising a plurality of multiplexers connected between the output lines and said sample and hold circuitry.

6. The device of claim 1, wherein said column decoder provides first addresses to said sample and hold circuit, the first addresses corresponding to columns within said first panel.

7. The device of claim 6, wherein said column decoder provides second addresses to said sample and hold circuit, the second addresses corresponding to columns within said second panel.

8. The device of claim 1, wherein said stored signals comprise reset and pixel signals from said first and second panels.

9. The device of claim 1, wherein said pixels are CMOS imaging pixels.

10. An imaging device comprising:

first and second panels of pixels, each panel being organized into a plurality of rows and columns;

first means for activating the rows of said first panel;

second means for activating the rows of said second panel, said first and second activating means respectively and independently activating rows within said first and second panels;

sample and hold means for sampling and holding signals from said first and second panel; and

means for controlling said sample and hold means such that pixel readout and column readout operations are pipelined.

11. The device of claim 10, wherein said pixels of each row are organized into pairs and each pair shares readout circuitry and a respective output line.

12. The device of claim 11 further comprising a plurality of multiplexers connected between the output lines and said sample and hold means.

13. The device of claim 10, wherein said pixels in each row are organized into pairs, each pair of pixels in a first row is associated with a pair of pixels in an adjacent row and shares readout circuitry and a respective output line with the associated pair.

14. The device of claim 13 further comprising a plurality of multiplexers connected between the output lines and said sample and hold means.

15. The device of claim 10, wherein said controlling means comprises a column decoder that provides first addresses to said sample and hold circuit means, the first addresses corresponding to columns within said first panel.

16. The device of claim 15, wherein said column decoder provides second addresses to said sample and hold means, the second addresses corresponding to columns within said second panel.

17. An imaging device comprising:

at least two panels of pixels, each panel being organized into a plurality of rows and columns; and

a pipeline readout circuit for providing the readout of rows of pixels from said panels.

18. A processor system comprising:

a processor; and

an imaging device coupled to said processor, said imaging device comprising;

an array of pixels comprising first and second panels, each panel being organized into a plurality of rows and columns,

a first row decoder connected to the rows of said first panel,

a second row decoder connected to the rows of said second panel, said first and second row decoders being configured to respectively and independently activate rows within said first and second panels,

sample and hold circuitry connected to the columns of the first and second panels, and

a column decoder connected to said sample and hold circuitry, said column decoder being controlled to address said sample and hold circuitry such that pixel readout from the first and second panels and column readout of stored signals are pipelined.

19. The system of claim 18, wherein said pixels of each row are organized into pairs and each pair shares readout circuitry and a respective output line.

20. The system of claim 19 further comprising a plurality of multiplexers connected between the output lines and said sample and hold circuitry.

21. The system of claim 18, wherein said pixels in each row are organized into pairs, each pair of pixels in a first row is associated with a pair of pixels in an adjacent row and shares readout circuitry and a respective output line with the associated pair.

22. The system of claim 21 further comprising a plurality of multiplexers connected between the output lines and said sample and hold circuitry.

23. The system of claim 18, wherein said column decoder provides first addresses to said sample and hold circuit, the first addresses corresponding to columns within said first panel.

24. The system of claim 23, wherein said column decoder provides second addresses to said sample and hold circuit, the second addresses corresponding to columns within said second panel.

25. The system of claim 18, wherein said stored signals comprise reset and pixel signals from said first and second panels.

26. The system of claim 18, wherein said pixels comprise CMOS imaging pixels.

27. A processor system comprising:

a processor; and

an imaging device coupled to said processor, said imaging device comprising;

first and second panels of pixels, each panel being organized into a plurality of rows and columns,

first means for activating the rows of said first panel,

second means for activating the rows of said second panel, said first and second activating means respectively and independently activating rows within said first and second panels,

sample and hold means for sampling and holding signals from said first and second panel, and

means for controlling said sample and hold means such that pixel readout and column readout operations are pipelined.

28. A processor system comprising:

a processor; and

an imaging device coupled to said processor, said imaging device comprising;

at least two panels of pixels, each panel being organized into a plurality of rows and columns; and

a pipeline readout circuit for providing the readout of rows of pixels from said panels.

29. A method of operating an imaging device, said method comprising the acts of:

reading out signals from first pixels within a first panel of pixels;

reading out signals from second pixels within a second panel of pixels; and

outputting stored signals from each column in the panels,

wherein said reading and outputting steps are pipelined.

30. The method of claim 29, wherein said step of reading out signals from first pixels comprises:

reading out reset signals from the first pixels; and

reading out pixel signals from the first pixels.

31. The method of claim 30, wherein said step of reading out signals from second pixels comprises:

reading out reset signals from the second pixels; and

reading out pixel signals from the second pixels.

32. The method of claim 29, wherein the first pixels of the first panel are organized into pairs and said step of reading out signals from first pixels comprises:

reading out reset signals from a first pixel of each pair of first pixels;

reading out reset signals from a second pixel of each pair of first pixels;

reading out pixels signals from the first pixel of each pair of first pixels; and

reading out reset signals from a second pixel of each pair of first pixels.

33. The method of claim 29, wherein the second pixels of the second panel are organized into pairs and said step of reading out signals from second pixels comprises:

reading out reset signals from a first pixel of each pair of second pixels;

reading out reset signals from a second pixel of each pair of second pixels;

reading out pixels signals from the first pixel of each pair of second pixels; and

reading out reset signals from a second pixel of each pair of second pixels.

34. A method of operating an imaging device, said method comprising the acts of:

reading out signals from a current row of first pixels associated with a first panel of pixels;

outputting stored signals from a previous row of second pixels associated with a second panel of pixels,

reading out signals from a current row of second pixels;

outputting stored signals from the current row of first pixels;

reading out signals from a next row of first pixels; and

outputting stored signals from the current row of second pixels.

35. A method of integrating an imaging device, said method comprising:

fabricating an array of pixels in at least two panels; and

fabricating a readout circuit coupled to the panel, the readout circuit enabling pipelined readout of the panels.