Non-volatile memory device

• US 20060007772A1
• Filed: 07/25/2005
• Published: 01/12/2006
• Est. Priority Date: 03/19/2002
• Status: Abandoned Application

• Current Assignee: O2ic, Inc.
• Original Assignee: O2ic, Inc.
• Inventors: Choi, Kyu Hyun
• Application Number:
  US11/189,548
• Publication Number:
  US 20060007772A1
• Time in Patent Office: Days
• US Class Current: 365/232
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down

Abstract

A non-volatile memory device includes a guiding gate that extends along a first portion of the device'"'"'s channel length and a control gate that extends along a second portion of the device'"'"'s channel length. The first and second portions of the channel length do not overlap. The guiding gate, which overlays the substrate above the channel region, is insulated from the semiconductor substrate in which the device is formed via an oxide layer. The channel region under the guiding gate has a doping concentration greater than the doping concentration of the substrate. The remaining portion of the channel region has a doping concentration greater than the doping concentration of the substrate but less than the doping concentration of the channel region under the guiding gate. The control gate, which also overlays the substrate above the channel region, is insulated from the substrate via an oxide-nitride-oxide layer.

Claims

1. A semiconductor device comprising:

a substrate region;

a source region formed in the substrate region;

a drain region formed in the substrate region and separated from the source region by a channel region;

a first gate overlaying a first portion of the channel and separated therefrom via a first insulating layer;

a second gate overlaying a second portion of the channel and separated therefrom via a second insulating layer;

wherein said first portion of the channel and said second portion of the channel do not overlap, wherein the first portion of the channel has an implant doping concentration that is greater than the implant doping concentration of a remainder portion of the channel region, wherein the remainder portion of the channel region has an implant doping concentration that is greater than the substrate doping concentration.

2. The semiconductor device of claim 1 wherein said first insulating layer is an oxide layer.

3. The semiconductor device of claim 2 wherein said second insulating layer further comprises a first oxide layer formed over said channel region, a first nitride layer formed over said first oxide layer of the second insulating layer, and a second oxide layer formed over said first nitride layer.

4. The semiconductor device of claim 3 wherein said first oxide layer of the first insulating layer is thinner than the first oxide layer of the second insulating layer.

5. The semiconductor device of claim 3 wherein said first oxide layer of the first insulating layer is thicker than the first oxide layer of the second insulating layer.

6. The semiconductor device of claim 4 wherein said first gate extends partially over the second gate.

7. The semiconductor device of claim 5 wherein said second gate extends partially over the first gate.

8. The semiconductor device of claim 6 wherein said device is programmed by applying a first voltage between the second gate and the substrate region, a second voltage between the first gate and the substrate region, and a third voltage between the source and the drain regions, said applied voltages causing electrons to be trapped in the nitride layer due to hot electron injection.

9. The semiconductor device of claim 8 wherein said electrons are trapped near the source region of the semiconductor device.

10. The semiconductor device of claim 9 wherein a channel connecting the source region to the drain region is formed in the substrate region while the device is being programmed.

11. The semiconductor device of claim 8 wherein said programmed device is erased by applying a fourth voltage to the second gate, a fifth voltage to the drain region and floating the first gate, said applied voltages causing the electrons trapped in nitride layer to tunnel to the substrate region or causing holes be trapped in the nitride layer to neutralize the trapped electrons.

12. The semiconductor device of claim 8 wherein said programmed device is erased by applying a fourth voltage to the second gate, a fifth voltage to the drain region and applying one of zero and negative voltage to the first gate, said applied voltages causing the electrons trapped in nitride layer to tunnel to the substrate region or causing holes be trapped in the nitride layer to neutralize the trapped electrons.

13. The semiconductor device of claim 7 wherein said device is programmed by applying a first voltage between the second gate and the substrate region, a second voltage between the first gate and the substrate region, and a third voltage between the source and the drain regions, said applied voltages causing electrons to be trapped in the nitride layer due to hot electron injection.

14. The semiconductor device of claim 13 wherein said electrons are trapped near the source region of the semiconductor device.

15. The semiconductor device of claim 14 wherein a channel connecting the source region to the drain region is formed in the substrate region while the device is being programmed.

16. The semiconductor device of claim 13 wherein said programmed device is erased by applying a fourth voltage to the second gate, a fifth voltage to the drain region and floating the first gate, said applied voltages causing the electrons trapped in nitride layer to tunnel to the substrate region or causing holes be trapped in the nitride layer to neutralize the trapped electrons.

17. The semiconductor device of claim 1 wherein said substrate region is a p-type region formed in a n-well region.